From January 20 to 23, HiPEAC25 took place Palau de Congressos de Barcelona in Barcelona, Spain. Our team from BSC was at the booth #21, answering questions about the road so far in the European Processor Initiative and showcasing EPAC - European Processor Accelerator demo.
In addition to that, colleagues from E4 Computer Engineering SpA and Barcelona Supercomputing Center organized a workshop titled "RISC-V: the cornerstone ISA for the next generation of HPC infrastructures”. There, our colleague from BSC, Pablo Vizcaino, presented his paper titled “RAVE: The RISC-V Analyzer of Vector Executions”.
Alexandra Kourfali from EuroHPC Joint Undertaking (EuroHPC JU) gave an overview of EuroHPC RISC-V initiatives.
