Accelerator Stream

The Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.

The EPAC basic building block is a tile containing up to 8 vector processors and specialized units. The processors are coherent, sharing L2 cache banks through a Network-on-Chip, each bank with its associated Home Node agent. through a Network-on-Chip. The processors will support RISC-V vector instructions, and will also control the specialised units dedicated to Stencil and Deep Learning acceleration. The vector and stencil capabilities will address HPC workloads, while the Deep-Learning units will target AI applications.

The vector processor architecture  will be based on these guiding principles:

  • Holistic throughput-oriented vision based on long vectors and task-based models
  • Hierarchical concurrency and locality exploitation
  • Communication between programming levels
  • Make it all look very close to classical sequential programming to ensure productivity

The dedicated unit architecture, on the other hand, will be geared towards a few specific applications. This specificity will be leveraged to explicitly manage the data placement and transfer from and into local scratchpad memories, targeting high-energy efficiency

The EPAC tile will be integrated both as a node in the GPP mesh, and as a stand-alone Test Chip for demonstration and software debugging purposes.

Compiler Explorer – Overview

The compiler team at the Barcelona Supercomputing Center working on EPI have setup of a Compiler Explorer for an LLVM-based compiler that targets the RISC-V and the V-extension (still draft) architecture.

Compiler Explorer is an open-source web application for interactive compiler code generation observation.

We want to use this tool to ease the analysis and study of the compiler code generation when targeting the RISC-V V-extension. This gives us valuable information in co-design as it can quickly expose pain points in the code generation. These pain points may suggest changes in the V-extension architecture or require new code generation strategies or optimizations in the compiler.

Compiler Explorer is intended for small programs or snippets not for large applications.

We have also integrated our own user-space functional emulator `vehave`. This emulator traps the vector extension instructions emitted by the compiler and emulates them with scalar instructions. This way we can execute vector applications and check their correctness under a RISC-V Linux environment. Both real hardware, such as the HiFive Unleashed, or `qemu-user` can be used. Our Compiler Explorer uses `qemu-user`.

Compiler Explorer website is

Compiler user guide is available here: user-guide-compiler-explorer

VaRiable Precision Processor VRP

The VaRiable Precision Unit enables efficient computation in scientific domains with extensive use of iterative linear algebra kernels, such as physics and chemistry. Augmenting accuracy inside the kernel reduces rounding errors and therefore improves computation’s stability. Usual solutions for this problem have a very high impact in memory and computation time (e.g. use double precision in the intermediate calculations).

The hardware support of variable precision, byte-aligned data format for intermediate data optimizes both memory usage and computing efficiency. When the standard precision unit cannot reach the expected accuracy with standard precision (aka double), the variable precision unit takes the relay and continues with gradually augmenting precision until the tolerance error constraint is met. The offloading from the host processor (GPP) to the VRP unit is ensured with zero-copy hadnover thanks to IO-coherency between EPAC and GPP.

The VRP is embedded as a functional unit in a 64-bits RISC-V processor pipeline. The unit extends the standard RISC-V Instruction with hardwired arithmetic basic operations in variable precision for scalars: add, subtract, multiply and type conversions. It implements other additional specific instructions for comparisons, type conversion and transfers to cache. The unit features a dedicated register file for storing up to 32 scalars with up to 256 bits of mantissa precision. Its architecture is pipelined for performance, and it has an internal parallelism of 64-bits. Thus, internal operations with higher precisions multiple of 64 bits are executed by iterating on the existing hardware.

The VRP programming model is meant for smooth integration with legacy scientific libraries such as BLAS, MAGMA and linear solver libraries. The integration in the host memory hierarchy is transparent for avoiding the need of data copy, and the accelerator offers a standard support of C programs. The libraries are organized in order to expose the variable precision kernels as compatible replacements of their usual counterparts in the BLAS and solver libraries. The complexity of arithmetic operations is confined as much as possible within the lower level library routines (BLAS). Consistently, the explicit control of precision is exclusively handled at solver level.

Stencil/tensor accelerator STX

From the beginning, EPI explicitly considered “specialised blocks for stencil and deep learning (DL) acceleration. The vector and stencil capabilities will address workloads in HPC centres, while the DL block will target learning acceleration” as part of the acceleration stream motivated by “optimised performance and energy efficiency” for “specialised computations”. In the initial DoA, two different domain-specific accelerators (NTX for machine learning, and a stencil accelerator) were suggested. During the first few months of the project, researchers from Fraunhofer Institute, ETH Zürich and University of Bologna were able to merge the functionality of both units into a very efficient computation engine that has been named STX (stencil/tensor accelerator).

Such “domain-specific accelerators” are now a major trend in industry, as can be seen by multiple new announcements in the 2019 Hot-Chips symposium and AI Summit by industry heavyweights as a multitude of startups that have presented acceleration engines that were based on specialised datapaths and not general purpose vector units, confirming the significant differentiation in architecture needed for achieving top efficiency and performance in the machine learning domain.

The main goal of STX is to achieve a significantly higher (at least 5x-10x) energy efficiency over general purpose/vector units. The efficiency tells us how many computations can be performed with the unit, and the early target for the STX unit was to achieve at least 5x more energy efficiency (TFLOPS/W) than the vector unit on deep learning applications. In the first few months of the project, it became clear that these estimations are rather conservative, and the effective efficiency within EPI chips will be significantly higher. For applications that require only inference using quantized networks, this efficiency will be another 10x higher.

STX has been designed as a modular building block with several parametrization options. Each STX accelerator consists of several clusters of computing units, a typical instance would have four such clusters. Each cluster in turn consists of specialised computing engines as well as up to two RISC-V cores that are used to control the computing engines and perform additional operations. All these units will access a local scratchpad memory, which will be filled using a centralized DMA unit. This configuration allows for 64 GFLOPS (single precision FP), and multiple instances of STX can be instantiated in an EPAC tile.

STX is programmed using OpenMP, there are solutions that allow regular operations to be offloaded to the STX unit from an Arm system (in the GPP) or the 64-bit RISC-V core (in the EPAC tile) using both GCC and LLVM based flows that will be fruther refined as part of the project.




Live News

#ACACES2023 has started🥰 Take a look at interesting courses, especially the one from Filippo Mantovani "A RISC-V vector CPU for High-Performance Computing: architecture, platforms and tools to make it happen" @hipeac @pilot_euproject @EUPEX_pilot
10/07/2023 08:50:00
RT @BSC_CNS: 🚀The ACM Europe Summer School on #HPC Computer Architectures for #AI & Dedicated Applications kicks off! 💻Hosted by BSC & @la…
06/07/2023 22:53:00
Want to know more about EUPILOT ? Check out this video to 👀 and 👂 it in 2 minutes!
06/07/2023 10:21:00
EPI keynote was carefully👂listened to today by the interested audience 👀 at the #ASHPC23 – Austrian-Slovenian HPC Meeting at the Institute of Information Science in Maribor (IZUM), Slovenia @eurocc_austria @VSCluster @uniinnsbruck @EuroCC_SLING @COBISSNET
15/06/2023 13:55:00
@euprocessor CCO Mario Kovač will present EPI in a keynote on the #ASHPC23 – Austrian-Slovenian HPC Meeting on the June 15 at the Institute of Information Science in Maribor (IZUM), Slovenia @eurocc_austria @VSCluster @uniinnsbruck @EuroCC_SLING @COBISSNET
14/06/2023 16:54:00
01/06/2023 14:14:00
Philippe Notton, CEO of #SiPearl is at the Conference on deep tech entrepreneurship in Stockholm, and will talk in one hour in the plenary session "Deep dive into the challenge of collaboration between small research-intensive companies, large companies, and academia" Watch live
01/06/2023 14:14:00
Interesting talk between @EuProcessor General Manager Etienne Walter and #SiPearl Vice President Marketing & Business Development Craig Prunty today at booth #7 in the Europa Village at #TeratecForum 👍 There is still time to visit our booth till the end of the day! @Teratec_EU
01/06/2023 12:28:00
The Teratec 2023 Forum has just started, visit us today and tomorrow at booth #7 📷in the Europa Village, Paris 🇫🇷. We will be close to our dear neighbours @EUPEX_pilot #TeratecForum @Teratec_EU
31/05/2023 09:05:00
Yesterday we had two excellent BoF @ISChpc with our partners from @Evidenlive participating in "Arm HPC Software Ecosystem Maturity on Fresh, Capable Hardware" and from @BSC_CNS and @e4company in "RISC-V is HPC. Help Build Your Ecosystem" Hope that you also enjoyed them! 🪶
25/05/2023 15:11:00
RT @EUPEX_pilot: It's interview time on our #ISC23 booth! Carlos Puchol @BSC_CNS is presenting our 3 projects to @insideHPC @EuProcessor @…
25/05/2023 10:08:00
Always great in a good company of @pilot_euproject and @EUPEX_pilot, end of day 2, looking forward to new talks tomorrow, we'll keep you updated 📝
23/05/2023 17:42:00
In two hours 🕞⏱️ our general manager Etienne Walter will have a talk about EPI at @e4company if you are close come to the booth C323 #ISC23
23/05/2023 13:30:00
Our partners @istecnico @Unipisa and @FraunhoferITWM have a poster at #ISC23 "An FPGA-based platform to evaluate Posit arithmetic in next generation processors", check out what they wrote about the next generation of EPI accelerators. ⚡️
23/05/2023 12:19:00
RT @EuroHPC_JU: @EuroHPC_JU is developing innovative and sustainable #HPC technologies The low-power microprocessor (EPI SGA2) @EuProcesso…
22/05/2023 15:00:00
Today at 17:20 Daniele Gregori, CSO of @e4company, will talk about the HPC challenges and European projects solving them - @EuProcessor, Maelstrom, Admire and Textarossa. See you at #ISC23 Hall H, Booth K1001 ✔️
22/05/2023 14:32:00
The #ISC23 has started and we are waiting for you at booth A101 together with @EUPEX_pilot and @pilot_euproject 👀 @ISChpc @EuroHPC_JU
22/05/2023 08:59:00
Only 15 days left to the Teratec 2023 Forum, visit us on 31 May and 1 June in Paris 🇫🇷 in Europa village at booth 7. We will be just next to our good neighbours @EUPEX_pilot 👨‍👦‍👦 #TeratecForum @Teratec_EU
16/05/2023 11:09:00
Only 15 days to #ISC23 ⏲️⏳ We look forward to seeing you at ISC23 @ISChpc on booth A103, together with @EUPEX_pilot and @pilot_euproject.
10/05/2023 10:35:00
EPI was presented to representatives of the Croatian government and region Emilia Romagna @RegioneER that visited FER @fer_unizg where we discussed the EU's digital future and further cooperation possibilities in many areas @EuProcessor #EmiliaRomagna @institutrb @HPCfer
04/05/2023 20:27:00
EPI Team is wishing you all a happy #Easter2023! 🥚💐
07/04/2023 11:09:00
RT @EuroHPC_JU: 📰 The news is out! 📣 @SiPearl, the 🇫🇷🇪🇺 French company building Rhea, the energy-efficient #HPC #microprocessor for exasca…
06/04/2023 11:18:00
EPI team had a succesful second Periodic Review in Luxembourg! 💪 Congratulations to all of our partners 😊
31/03/2023 15:17:00
We had a great time at the #EuroHPCSummit2023 in Sweden! 🦾 Thank to all of you who visited us at the poster session and who attended session with Mario Kovač (@HPCfer) in organisation with @Etp4HPC 😁
24/03/2023 13:10:00
The summer school addresses young computer science researchers and engineers and is open to outstanding MSc students. Accepted students will spend one week in Barcelona, attending formal lectures, invited talks, and other activities. 🤓
23/03/2023 15:32:00
.@TheOfficialACM Summer School on HPC Computer Architectures for AI and Dedicated Applications, co-hosted by @BSC_CNS and @la_UPC invites you to register until April 15th! ⏰ More about the summer school and registrations here ⬇️
23/03/2023 15:31:00
RT @Etp4HPC: Our 2nd session of the afternoon is starting at #EuroHPCSummit2023 with Mario Kovac from @EuProcessor We're in room 3, join u…
22/03/2023 17:01:00
The #EuroHPCSummit2023 is finally here! 🦾 We look forward to interesting discussions and seeing our colleagues who work on interesting projects. Don't forget to visit us today at the project poster session! 😁
20/03/2023 13:47:00
📣 Join us in the project poster session at #EuroHPCSummit2023! Learn more about our project and our plans for the future. We look forward to seeing you in Sweden in just 4 days! 💪
16/03/2023 12:04:00
Mario Kovač (@HPCfer) will have a keynote speech related to the EPI project today at HPC, Data & Architecture Week in Buenos Aires, Argentina. 🇦🇷 More information about the event here ➡️
13/03/2023 12:31:00
RT @Etp4HPC: 1 week to #EuroHPCSummit2023 ! Don’t miss the 2 sessions run by ETP4HPC on 22 March: 14:30 Emerging Technologies for HPC in Eu…
13/03/2023 10:47:00
The @EuroHPC_JU Summit is approaching! Mario Kovač from @HPCfer will participate in a session "Towards an Autonomous European HPC Supply Chain: Showcasing EuroHPC Projects." EPI will also be present in the poster session. ➡️ See you in Sweden! 🇸🇪
06/03/2023 09:40:00
📢 EPI will be a sponsor of the 2023 edition of @TheOfficialACM Summer School on HPC Computer Architectures for AI and Dedicated Applications, co-hosted by @BSC_CNS and @la_UPC. More about the summer school and registrations here 👇
01/03/2023 14:51:00
RT @hipeac: How is Europe’s quest for a homegrown processor going? We asked Étienne Walter @Atos @EuProcessor #HiPEAC23 #HiPEACTV @EuroHPC…
24/02/2023 14:47:00
RT @Kalrayinc: 📢 Don't miss @Kalrayinc's Keynote at SuperComputing Asia 2023 (#SCA2023)! Benoit Dupont de Dinechin, Kalray's CTO, will tal…
23/02/2023 18:27:00
Étienne Walter (@Atos) spoke to @hipeac about the next steps for the European Processor Initiative. 👀 You can watch the interview here ⬇️
22/02/2023 14:07:00
Manolis Marazakis from @FORTH_ITE had a keynote at the @hipeac conference (RAPIDO workshop) where he presented "Challenges in modelling HPC SoCs: An experience report on using Gem5." More information about the workshop here:
20/01/2023 09:53:00
We would like to thank everyone who participated in our "EPI Tutorial" at the @hipeac conference! 🥳 In addition, we would like to thank our partners @CEA_Officiel, @fzj_jsc, @BSC_CNS and @HPCfer for creating this tutorial💪🏻 #HiPEAC23
18/01/2023 17:10:00
RT @hipeac: 🎸HiPEAC rocks! Day 2 of #HiPEAC23: industry meets academia, students meet former employers. What did you get up to? 👉 https://…
18/01/2023 17:00:00
Today is the last day of the @hipeac conference in Toulouse! Take the opportunity to visit us at booth 14 and learn more about our project. 🦾 #HiPEAC23
18/01/2023 10:18:00
We had a great time at the @hipeac conference yesterday and look forward to today's sessions! 😁 Our team is waiting for you at booth 14 🤓
17/01/2023 10:55:00
RT @fdrcrss: #HiPEAC2023 - Giving a #keynote at @hipeac today at 12:30!
17/01/2023 10:51:00
RT @hipeac: From atoms to applications: find out what we got up to on day 1 of #HiPEAC23, ft. Albert Cohen and Subhasish Mitra 📺 https://t…
17/01/2023 10:50:00
@PCzanik @hipeac Thank you for following and supporting us! We will have an announcement and timeline really soon.
16/01/2023 16:05:00
@PCzanik @hipeac Dear Peter, thank you very much for your question! 😊 We will soon make an announcement regarding your question on the EPI website. In addition, we have an RSS feed where you can follow the project news easier:
16/01/2023 14:19:00
We love to use conferences like #HiPEAC23 to network and meet with our partners and representatives of other initiatives!🦾
16/01/2023 13:54:00
Join us today at @hipeac conference in Toulouse! 💪 You can find us at booth 14, our team looks forward to your questions 😊
16/01/2023 11:11:00
RT @heroes_hpc: Ready for @hipeac 2023 in Toulouse? 🇫🇷 📌Don’t miss our HEROES talk today at 12:00 in the CONCERTO workshop. @HPC_Now partn…
16/01/2023 09:36:00
Save the date for the EPI Tutorial at the @hipeac conference! 🗓️ #HiPEAC23 On Monday you will have the opportunity to participate in a tutorial organised by EPI partners @CEA_Officiel, @fzj_jsc, @BSC_CNS and @fer_unizg! 🦾 More information here ➡️
13/01/2023 12:48:00
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