Accelerator

Accelerator Stream

The Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.

The EPAC basic building block is a tile containing up to 8 vector processors and specialized units. The processors are coherent, sharing L2 cache banks through a Network-on-Chip, each bank with its associated Home Node agent. through a Network-on-Chip. The processors will support RISC-V vector instructions, and will also control the specialised units dedicated to Stencil and Deep Learning acceleration. The vector and stencil capabilities will address HPC workloads, while the Deep-Learning units will target AI applications.

The vector processor architecture  will be based on these guiding principles:

  • Holistic throughput-oriented vision based on long vectors and task-based models
  • Hierarchical concurrency and locality exploitation
  • Communication between programming levels
  • Make it all look very close to classical sequential programming to ensure productivity

The dedicated unit architecture, on the other hand, will be geared towards a few specific applications. This specificity will be leveraged to explicitly manage the data placement and transfer from and into local scratchpad memories, targeting high-energy efficiency

The EPAC tile will be integrated both as a node in the GPP mesh, and as a stand-alone Test Chip for demonstration and software debugging purposes.

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Live News

EPI First tutorial held in Barcelona

Partners from the European Processor Initiative organized and held their first public tutorial on EPI called “First steps towards a made-in-Europe high-performance microprocessor”. It was held on July 17th, at the Universita Politècnica de Catalunya, co-located with the ACM 2019 Summer school on HPC architectures for AI and dedicated applications. EPI distinguished experts presented in […]
2019-07-20
Last segment of tutorial: Jaume Abella from @BSC_CNS talking about the #Automotive domain of EPI. https://t.co/Xy3xi7ZGFy
17/07/2019 2:45 pm
@OdnetninI @BSC_CNS We will try and make available all the lectures on our channel soon!
17/07/2019 2:05 pm
EPI software on the menu: Jesus Labarta is explaining EPI hierarchical system. @BSC_CNS https://t.co/R24geQ4KRv
17/07/2019 1:56 pm
@Mauro_Olivieri_ We thought we'd show proof you found the room on time 😄. Starting the #accelerator segment of the EPI tutorial! @BSC_CNS https://t.co/TB00JzvYmI
17/07/2019 1:14 pm
@_abartolini_ is presenting the new challenges of the #HPC #processors at the first EPI #tutorial. @BSC_CNS @la_UPC @UniboMagazine https://t.co/PJKrSTm5j5
17/07/2019 12:25 pm
Fabrizio Gagliardi from @BSC_CNS opening the first tutorial on EPI! https://t.co/vb5xiHTJS4
17/07/2019 12:14 pm
@Mauro_Olivieri_ @la_UPC @BSC_CNS Happy to be of service with subtle reminders 😁☝️
17/07/2019 9:46 am
In less than 3 hours, the first EPI #tutorial is beginning at Sala Àgora, @la_UPC. Our @BSC_CNS staff is getting everything ready to welcome the first group of students and applicants in what we hope is the first of many more EPI tutorials. Soo exciting 🎉! Stay tuned! https://t.co/YCBZ3P0syu
17/07/2019 9:31 am

EPI’s first tutorial – July 17

EPI will hold it's first tutorial on July 17th 2019 in Barcelona.
2019-06-10
Different competences and perspective, coming from the diversity of 26 partners in EPI 🇪🇺 https://t.co/aOPAkaSAXY
14/07/2019 5:44 pm
@Mauro_Olivieri_ on why Europe needs its processor: security, economic problems, sovereignty! @hipeac https://t.co/Sx5AAJVFjZ
14/07/2019 5:23 pm

EPI’s Manager on NVIDIA Bringing CUDA to Arm

NVIDIA announced its support for Arm CPUs, by making available to the Arm® ecosystem its full stack of AI and HPC software — which accelerates more than 600 HPC applications and all AI frameworks – by year’s end. The stack includes all NVIDIA CUDA-X AI™ and HPC libraries, GPU-accelerated AI frameworks and software development tools such as […]
2019-06-17

First steps towards a made-in-Europe high-performance microprocessor

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2019-06-04

EPI at EuroHPC Summit Week

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2019-05-22

EPI Presented at Barcelona RISC-V Workshop

Prof. Mateo Valero, director of the Barcelona Supercomputing Center, presented the European Processor Initiative in RISC-V Workshop, Barcelona 7-10 May, 2018. His keynote focused on the role of RISC-V architecture in the EPI project and in future exascale computing systems in general. Video is available here
2019-04-24

European Processor Initiative kicks off in Brussels

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2019-04-24

EPI presented in HPC User Forum, Detroit 2018

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2019-04-24

European Processor Initiative announced on European Commission website

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2019-04-24

EFECS

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2019-04-24