The Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.
The EPAC basic building block is a tile containing up to 8 vector processors and specialized units. The processors are coherent, sharing L2 cache banks through a Network-on-Chip, each bank with its associated Home Node agent. through a Network-on-Chip. The processors will support RISC-V vector instructions, and will also control the specialised units dedicated to Stencil and Deep Learning acceleration. The vector and stencil capabilities will address HPC workloads, while the Deep-Learning units will target AI applications.