Accelerator

Accelerator Stream

The Accelerator stream will develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator tiles within the GPP chip. Using RISC-V allows leveraging open source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.

The EPAC basic building block is a tile containing up to 8 vector processors and specialized units. The processors are coherent, sharing L2 cache banks through a Network-on-Chip, each bank with its associated Home Node agent. through a Network-on-Chip. The processors will support RISC-V vector instructions, and will also control the specialised units dedicated to Stencil and Deep Learning acceleration. The vector and stencil capabilities will address HPC workloads, while the Deep-Learning units will target AI applications.

The vector processor architecture  will be based on these guiding principles:

  • Holistic throughput-oriented vision based on long vectors and task-based models
  • Hierarchical concurrency and locality exploitation
  • Communication between programming levels
  • Make it all look very close to classical sequential programming to ensure productivity

The dedicated unit architecture, on the other hand, will be geared towards a few specific applications. This specificity will be leveraged to explicitly manage the data placement and transfer from and into local scratchpad memories, targeting high-energy efficiency

The EPAC tile will be integrated both as a node in the GPP mesh, and as a stand-alone Test Chip for demonstration and software debugging purposes.

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Live News

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08/11/2019 5:43 am
RT @primeurmagazine: Interview with @EuProcessor European Processor Initiative's @JeanMarc_Denis about the development and architecture. #E…
05/11/2019 8:16 am
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04/11/2019 11:02 am

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2019-11-04
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28/10/2019 5:19 pm
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28/10/2019 12:44 pm
EPI Accelerator (EPAC) partners met in #Mannheim at EXTOLL for the first integration of components: #RISC-V core, NoC, L2 Cache and Home Node. Happy faces😃 https://t.co/nakCJALfgS
22/10/2019 7:19 am

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2019-10-18
RT @hipeac: 📢HiPEAC Technology Transfer Awards 2019 - apply now! ❓Successfully transferred your research to the market? 💡Licensed your tec…
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If you happen upon #IEEE I&M chapter's #GDR #SoC #Workshop in Nancy, France, our very own Sergio Saponara is presenting! 👉 https://t.co/GWpBfiSH7n
10/10/2019 10:35 am
@pulp_platform Bianca is wired to attend the workshop 😁 #BadPunThursday
10/10/2019 9:41 am
What's that our colleague is holding? An EPI flyer, you say? In close proximity to candy? 😃 Come meet our colleagues from Menta company and talk EPI with them, they are at the @Arm #TechCon in San Jose, working their booth tirelessly! https://t.co/xrHKASevXo
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2019-07-20

EPI activities in events

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EPI’s first tutorial – July 17

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2019-06-10

EPI’s Manager on NVIDIA Bringing CUDA to Arm

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2019-06-17

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2019-05-22

EPI Presented at Barcelona RISC-V Workshop

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2019-04-24

EPI presented in HPC User Forum, Detroit 2018

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2019-04-24