The eFPGA tile, which is integrated into the General Purpose Processor chip (GPP), contributes to an energy-effiient allocation of the necessary perfomrance by an optimal internaction wiht the main CPU and the dedicated Hardware accelrators.
Menta eFPGA IP is optimized for feneral purpose HPC and automotive applications such as image-processing using machine learning (ML). It allows post-prodcution functions ike customer customization and proprietary elements. In addition, it can consider emerging security aspets, like run-time reconfigurable crypto and post quantum public crypto accelerators.
The eFPGA core plays a key role in an optimal hardware/software codesign system, enabling reconfigruation options for the next geenration of European HPC and automotive industry.
Hardware acceleration features are moved on-chip, without the limitations or overhead due I/O pad-count or chip-to-chip communication interfaces. The eFPGA core is provided to EPI customers with the corresponding programming softrware-tool, Origami Programmer, which generates the bitstream that targets and optimizes RTL to the needs of Menta eFPGA architecture. The technology does not rely on third party software tools, which target generic FPGA architecture and thus deliver suboptimal results.