The eFPGA tile, which is integrated into the General Purpose Processor chip (GPP), contributes to an energy-efficient allocation of the necessary performance by an optimal interaction with the main CPU and the dedicated Hardware accelerators.
Menta eFPGA IP is optimized for general purpose HPC and automotive applications such as image-processing using machine learning (ML). It allows post-production functions like customer customization and proprietary elements. In addition, it can consider emerging security aspects, like run-time reconfigurable crypto and post-quantum public crypto accelerators.
The eFPGA core plays a key role in an optimal hardware/software codesign system, enabling reconfiguration options for the next generation of the European HPC and automotive industry.
Hardware acceleration features are moved on-chip, without the limitations or overhead due to I/O pad-count or chip-to-chip communication interfaces. The eFPGA core is provided to EPI customers with the corresponding programming software-tool, Origami Programmer, which generates the bitstream that targets and optimizes RTL to the needs of Menta eFPGA architecture. The technology does not rely on third-party software tools, which target generic FPGA architecture and thus deliver suboptimal results.