EPI, therefore, intends to share a strong set of common technology across different application domains. Starting from the selection of cutting-edge process technology, a low-power design approach ranges from massive parallelism, specialized architecture, low-voltage operating point, and fine grain power management. The software stack will be designed to integrate and take advantage of these features to achieve high-energy efficiency and maximize performance across a wide range of layers from the low-level firmware, all the way up to system software and application run-times. For this purpose, EPI will harmonize the heterogeneous computing environment by defining a common approach: the so-called Common Platform (CP). It will include the global architecture (hardware and software) specification, common design methodology, and global approach for power management and security.
The CP is organized around a 2D-mesh Network-on-Chip (NoC) connecting computing tiles based on high-performance general-purpose CPU core with built-in FPU acceleration and specialized application-accelerators with different acceleration levels designed within EPI project.
A common software environment between heterogeneous computing tiles will harmonize the system as well as acting as a common backbone of IP components for IO connection with the external environment such as memories and interconnected or loosely coupled accelerators. With this CP approach, EPI will provide an environment that seamlessly integrates any computing tile. The right balance of computing resources for application matching will be defined through the ratio of the accelerator and general-purpose tiles.