Innovative Technology
General Purpose processor development
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GPP Stream

Exascale computation systems will need to simultaneously meet challenges related to performance, system cost, and energy efficiency. To deliver performance, a vast amount of resources is required, but the wrong choices of components, architecture, or implementation might result in a system which is much too expensive and too power-hungry. To find the right balance, global system level optimization is necessary.

EPI, therefore, intends to share a strong set of common technology across different application domains. Starting from the selection of cutting-edge process technology, a low-power design approach ranges from massive parallelism, specialized architecture, low-voltage operating point, and fine grain power management. The software stack will be designed to integrate and take advantage of these features to achieve high-energy efficiency and maximize performance across a wide range of layers from the low-level firmware, all the way up to system software and application run-times. For this purpose, EPI will harmonize the heterogeneous computing environment by defining a common approach: the so-called Common Platform (CP). It will include the global architecture (hardware and software) specification, common design methodology, and global approach for power management and security.

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The CP is organized around a 2D-mesh Network-on-Chip (NoC) connecting computing tiles based on high-performance general-purpose CPU core with built-in FPU acceleration and specialized application-accelerators with different acceleration levels designed within EPI project.

A common software environment between heterogeneous computing tiles will harmonize the system as well as acting as a common backbone of IP components for IO connection with the external environment such as memories and interconnected or loosely coupled accelerators. With this CP approach, EPI will provide an environment that seamlessly integrates any computing tile. The right balance of computing resources for application matching will be defined through the ratio of the accelerator and general-purpose tiles.

EPI embedded FPGA eFPGA

The eFPGA tile, which is integrated into the General Purpose Processor chip (GPP), contributes to an energy-effiient allocation of the necessary perfomrance by an optimal internaction wiht the main CPU and the dedicated Hardware accelrators.

Menta eFPGA IP is optimized for feneral purpose HPC and automotive applications such as image-processing using machine learning (ML). It allows post-prodcution functions ike customer customization and proprietary elements. In addition, it can consider emerging security aspets, like run-time reconfigurable crypto and post quantum public crypto accelerators.

The eFPGA core plays a key role in an optimal hardware/software codesign system, enabling reconfigruation options for the next geenration of European HPC and automotive industry.

Hardware acceleration features are moved on-chip, without the limitations or overhead due I/O pad-count or chip-to-chip communication interfaces. The eFPGA core is provided to EPI customers with the corresponding programming softrware-tool, Origami Programmer, which generates the bitstream that targets and optimizes RTL to the needs of Menta eFPGA architecture. The technology does not rely on third party software tools, which target generic FPGA architecture and thus deliver suboptimal results.




Live News

SiPearl, Industrial hand of EPI launches

SiPearl, EPI’s industrial and business hand, joins the EPI consortium as its 27th partner and moves into its operational phase. SiPearl and its solutions will help drive the development of the European market for high-performance computing (HPC), as well as its strategic applications such as artificial intelligence and connected mobility. SiPearl will develop and market […]
Francisco J. Cazorla and Hamid Tabani from @BSC_CNS are at the PhD school of DII @Unipisa with their host, prof. Sergio Saponara, holding a PhD course related to EPI research as well😃
23/01/2020 10:12 am
Some of EPI tutorial captains, still have strength to pose soccer-style, after a few hours of tutorial 😁. [Sadly, without @Mauro_Olivieri_ and Denis Dutoit in the picture, who had to rush away.] Thank you, @hipeac, for a fantastic conference, see you next time! #HiPEAC20
22/01/2020 5:48 pm
To finish the tutorial, our colleague from @BSC_CNS on the vector accelerator!
22/01/2020 3:13 pm
RT @e4company: "Empowering Europe towards the Exascale age": E4's talk at the @hipeac Conference 2020, inside the @EuProcessor tutorial. No…
22/01/2020 2:43 pm
Power management and controller in EPI, by @_abartolini_ #HIPEAC2020
22/01/2020 2:22 pm
Tutorial on EPI is still going on, @Mauro_Olivieri_ is explaining EPAC at #HiPEAC2020.
22/01/2020 1:57 pm
Full house at EPI tutorial at #HIPEAC2020, while Denis Dutoit from CEA is presenting: that's what we like to see!
22/01/2020 1:40 pm
22/01/2020 1:13 pm
Yesterday at #HIPEAC2020, Fabrizio Magugliani from @e4company presented EPI at the Industrial session, while today, make sure not to miss our full-on Tutorial at room Bianca B, starting at 14:00!
22/01/2020 9:07 am
We love a busy booth! But we especially love a booth busy with #STEM students ☺️. Meet us at booth 22 at #HIPEAC2020!
21/01/2020 9:32 am

European Processor Initiative: First year of activities

The project is finishing its first year with introduction of a new EPI Common Platform, an updated roadmap and presence at key events

Busy EPI partners in October

October started pretty busy for EPI partners, who attended various events presenting the latest from the Initiative.

EPI First tutorial held in Barcelona

Partners from the European Processor Initiative organized and held their first public tutorial on EPI called “First steps towards a made-in-Europe high-performance microprocessor”. It was held on July 17th, at the Universita Politècnica de Catalunya, co-located with the ACM 2019 Summer school on HPC architectures for AI and dedicated applications. EPI distinguished experts presented in […]

EPI activities in events

Last week has been loaded with activities for the European Processor Initiative. Our team attended several very important events, where EPI was discussed and our road to the low-power processor presented. EPI Chairman of the Board, Jean-Marc Denis, attended two events, in a Transatlantic hop, skip and a jump: first, the 73rd HPC User Forum […]

EPI’s first tutorial – July 17

EPI will hold it's first tutorial on July 17th 2019 in Barcelona.

EPI’s Manager on NVIDIA Bringing CUDA to Arm

NVIDIA announced its support for Arm CPUs, by making available to the Arm® ecosystem its full stack of AI and HPC software — which accelerates more than 600 HPC applications and all AI frameworks – by year’s end. The stack includes all NVIDIA CUDA-X AI™ and HPC libraries, GPU-accelerated AI frameworks and software development tools such as […]

First steps towards a made-in-Europe high-performance microprocessor

The European Processor Initiative (EPI), crucial element of the European exascale strategy, delivers its first architectural design to the European Commission and welcomes new partners Almost six months in, the project that kicked off last December has already delivered its first architectural designs to the European Commission, thus marking initial milestones successfully executed. The project […]

EPI at EuroHPC Summit Week

Impressions from the EuroHPC Summit Week 2019, that was held from 13 to 17 May in Poznań, Poland, are still fresh, as the event turned out a huge number of attendees and interesting topics covered in the 4-day event. European Processing Initiative, under the moderating lead of Mr Leonardo Flores Añover and Mr Andrea Feltrin […]

EPI presented in HPC User Forum, Detroit 2018

Jean-Marc Denis, HPC International Business Director at Bull, the EPI consortium coordinator, presents EPI at HPC User Forum in Detroit.