Innovative Technology
General Purpose processor development
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Next-generation General Purpose Processor (GPP) and Common Platform

The objective of this stream is to move forward with the development of the second-generation EPI microprocessor targeting future European exascale supercomputers by applying technological enhancements to the baseline of GPP Rhea from SGA1.

In parallel, this stream focuses on the development of an open Common Platform standard aiming to efficiently interface processors and accelerators in-package, implementing cache coherency, and validating the toolchains and runtime between processors and accelerators.

Preparing the Next-generation of General Purpose Processor

EPI effort in SGA1 included the definition and design of an HPC Microprocessor targeting V1 Arm cores, HBM, DDR5, PCIeG5/CXL/CCIX. Bringing together partners encompassing academia, research, industrials, system developers and system integrators, the EPI focus was a competitive and performant HPC Processor targeting IP largely from the market, to maximize the probability of first-time success bringing Rhea to market.

In SGA2, SiPearl and Stream 2 partners will increase performance by increasing the number of cores and memory bandwidth, adding in chip acceleration, and custom IP blocks. More specifically, the new generation GPP will uphold word-class competition by:

  • Addressing key CPU performance metrics including performance per socket, per Watt and per mm2, byte per FLOP ratio, and HPCG efficiency (i.e., the ratio between the HPCG performance and the peak performance)
  • Increasing the memory bandwidth
  • Implementing the latest interconnects such as CXL
  • Improving energy efficiency on key applications by updating the silicon process and the micro-architecture
  • Improving package integration through D2D interface driven by the common platform activities
  • Enforcing security with elements such as memory and link encryption, post-quantum cryptography
  • Preparing compliance readiness for CC EAL4+ certification
  • Offering a rich software ecosystem supporting the objectives of a software common platform.

Stream 2 will validate performance based on prototype boards that will be the basis for general-purpose compute nodes in large scale HPC systems.

Common Platform

In EPI SGA2, work on the “Common Platform” (common to the GPP & Accelerator streams) will be further developed at hardware and software levels in continuation of EPI SGA1.

Stream 2 will produce the specification that defines the hardware Common Platform for the chip and system integrating technologies to address the need for designing decoupled systems combining hybrid compute units, with closely coupled performance and ease of use.

Use cases will be studied to specify requirements for the hardware Common Platform Architectural specification. As part of these activities, interfaces such as the latest CXL, CCIX, and PCIe will be considered. Specifically, CXL will offer memory and I/O coherency, lower latency than PCIe and future proofing. Moreover, we will analyse die-to-die interfaces for chiplet-chiplet interconnects: BOW, UCIe, and XSR are some of the candidate solutions to be analysed for performance as well as expected industry acceptance and availability.

From a software perspective, the objectives of the Common Platform are to elaborate an ecosystem and a set of methods and tools to program accelerators seamlessly across socket-socket or die-to-die interfaces. This will be achieved by selecting or developing standards for connections between heterogeneous elements including software support for physical interconnects, SW orchestration, and support for memory coherency. This will enable the development of generic programming approaches that ensure code portability and performance portability, and ultimately aid performance testing on HPC platforms offering different processor technologies.

The expected achievements consist in aligning with, modifying, or building a standard for hardware Common Platform implementing the software flow to offload computing tasks to accelerator units and the related accelerator software flow.

Validation and Codesign

Stream 1 will bring up EPI’s first generation processor (Rhea 1) and board, then connect the EPI accelerator (EPAC v1.0/1.5) to the board via PCIe to build a hardware prototype on which software will be installed and applications ported. This will serve to validate the first generation of European processors targeted for the HPC market.

Simultaneously, a co-design process will take place targeting the second EPI generations (Rhea-2 and EPAC v2) chips to be developed in EPI. Application requirements will be collected and simulation-based architecture analysis performed to identify the best suited design parameters.


In EPI, processor development is driven by co-design, which is understood as a bi-directional and iterative interaction process between application owners, hardware, and system-software developers from Streams 2 and 3. The EPI benchmark suite, constituted by a wide variety of applications, mini-apps and synthetic benchmarks, is the basis for the characterization of the application-requirements. Quantitative user-requirements are determined running various elements of the benchmark suite on reference platforms, simulators, modelling tools, and emulation hardware. With these, the impact of specific design parameters into application’s performance, energy efficiency, and resiliency are studied. The benefits of given microarchitecture features in terms of time-to-solution and energy-to-solution are evaluated against cost-related considerations such as area or component price, and trade-off analysis are performed to find sweet spots where the chip design is frozen. The evaluation of Rhea and EPAC v1.0 will also provide valuable insight on the features that might need to be improved in the second-generation EPI products.

Bringup, Prototyping and Validation

State of the art techniques will be used to bring to life the Rhea processor and the Rhea reference board (Rhea REF) manufactured by Atos. A validation plan will be employed and updated to ensure the good quality of the products, and, if necessary, a new board revision will be triggered to fix all detected issues.

Once the functionality of the boards is verified, they will be integrated into engineering prototypes, on which low-level tests are run to verify its operation and stability, to then assemble them into a small-size cluster. The Rhea cluster, in which power distribution, cooling infrastructure, and sensors for safe operation are key elements, will be manufactured by E4 Computer Engineering and operated at their premises. It will contain up to 8 Rhea-REF boards, some of them hosting a PCIe-attached EPAC v1.0/v1.5 Daughter Board, to develop and test a GPP + ACCELERATOR environment. In parallel, a mini-cluster interconnecting up to 3 EPAC v1.0 accelerators will be assembled at BSC, and later upgraded to EPAC v1.5.

Remote access to the Rhea and EPAC clusters will be given to the validation team, once the complete compute software stack (from OS to programming environment and libraries) is installed on the systems. The validation team will use the EPI benchmark suite to run first small benchmarks on the prototype clusters, then mini-apps, and end up with full application codes. These tests will serve as stress tests for the clusters, informing also about their functionality, performance, ease of use, and reliability. In summary, these application runs will deliver the ultimate validation of the Rhea and EPAC v1.0/1.5 products, indicating whether they are ready for general deployment and qualified to build a large-scale HPC system.




Live News

#ACACES2023 has started🥰 Take a look at interesting courses, especially the one from Filippo Mantovani "A RISC-V vector CPU for High-Performance Computing: architecture, platforms and tools to make it happen" @hipeac @pilot_euproject @EUPEX_pilot
10/07/2023 08:50:00
RT @BSC_CNS: 🚀The ACM Europe Summer School on #HPC Computer Architectures for #AI & Dedicated Applications kicks off! 💻Hosted by BSC & @la…
06/07/2023 22:53:00
Want to know more about EUPILOT ? Check out this video to 👀 and 👂 it in 2 minutes!
06/07/2023 10:21:00
EPI keynote was carefully👂listened to today by the interested audience 👀 at the #ASHPC23 – Austrian-Slovenian HPC Meeting at the Institute of Information Science in Maribor (IZUM), Slovenia @eurocc_austria @VSCluster @uniinnsbruck @EuroCC_SLING @COBISSNET
15/06/2023 13:55:00
@euprocessor CCO Mario Kovač will present EPI in a keynote on the #ASHPC23 – Austrian-Slovenian HPC Meeting on the June 15 at the Institute of Information Science in Maribor (IZUM), Slovenia @eurocc_austria @VSCluster @uniinnsbruck @EuroCC_SLING @COBISSNET
14/06/2023 16:54:00
01/06/2023 14:14:00
Philippe Notton, CEO of #SiPearl is at the Conference on deep tech entrepreneurship in Stockholm, and will talk in one hour in the plenary session "Deep dive into the challenge of collaboration between small research-intensive companies, large companies, and academia" Watch live
01/06/2023 14:14:00
Interesting talk between @EuProcessor General Manager Etienne Walter and #SiPearl Vice President Marketing & Business Development Craig Prunty today at booth #7 in the Europa Village at #TeratecForum 👍 There is still time to visit our booth till the end of the day! @Teratec_EU
01/06/2023 12:28:00
The Teratec 2023 Forum has just started, visit us today and tomorrow at booth #7 📷in the Europa Village, Paris 🇫🇷. We will be close to our dear neighbours @EUPEX_pilot #TeratecForum @Teratec_EU
31/05/2023 09:05:00
Yesterday we had two excellent BoF @ISChpc with our partners from @Evidenlive participating in "Arm HPC Software Ecosystem Maturity on Fresh, Capable Hardware" and from @BSC_CNS and @e4company in "RISC-V is HPC. Help Build Your Ecosystem" Hope that you also enjoyed them! 🪶
25/05/2023 15:11:00
RT @EUPEX_pilot: It's interview time on our #ISC23 booth! Carlos Puchol @BSC_CNS is presenting our 3 projects to @insideHPC @EuProcessor @…
25/05/2023 10:08:00
Always great in a good company of @pilot_euproject and @EUPEX_pilot, end of day 2, looking forward to new talks tomorrow, we'll keep you updated 📝
23/05/2023 17:42:00
In two hours 🕞⏱️ our general manager Etienne Walter will have a talk about EPI at @e4company if you are close come to the booth C323 #ISC23
23/05/2023 13:30:00
Our partners @istecnico @Unipisa and @FraunhoferITWM have a poster at #ISC23 "An FPGA-based platform to evaluate Posit arithmetic in next generation processors", check out what they wrote about the next generation of EPI accelerators. ⚡️
23/05/2023 12:19:00
RT @EuroHPC_JU: @EuroHPC_JU is developing innovative and sustainable #HPC technologies The low-power microprocessor (EPI SGA2) @EuProcesso…
22/05/2023 15:00:00
Today at 17:20 Daniele Gregori, CSO of @e4company, will talk about the HPC challenges and European projects solving them - @EuProcessor, Maelstrom, Admire and Textarossa. See you at #ISC23 Hall H, Booth K1001 ✔️
22/05/2023 14:32:00
The #ISC23 has started and we are waiting for you at booth A101 together with @EUPEX_pilot and @pilot_euproject 👀 @ISChpc @EuroHPC_JU
22/05/2023 08:59:00
Only 15 days left to the Teratec 2023 Forum, visit us on 31 May and 1 June in Paris 🇫🇷 in Europa village at booth 7. We will be just next to our good neighbours @EUPEX_pilot 👨‍👦‍👦 #TeratecForum @Teratec_EU
16/05/2023 11:09:00
Only 15 days to #ISC23 ⏲️⏳ We look forward to seeing you at ISC23 @ISChpc on booth A103, together with @EUPEX_pilot and @pilot_euproject.
10/05/2023 10:35:00
EPI was presented to representatives of the Croatian government and region Emilia Romagna @RegioneER that visited FER @fer_unizg where we discussed the EU's digital future and further cooperation possibilities in many areas @EuProcessor #EmiliaRomagna @institutrb @HPCfer
04/05/2023 20:27:00
EPI Team is wishing you all a happy #Easter2023! 🥚💐
07/04/2023 11:09:00
RT @EuroHPC_JU: 📰 The news is out! 📣 @SiPearl, the 🇫🇷🇪🇺 French company building Rhea, the energy-efficient #HPC #microprocessor for exasca…
06/04/2023 11:18:00
EPI team had a succesful second Periodic Review in Luxembourg! 💪 Congratulations to all of our partners 😊
31/03/2023 15:17:00
We had a great time at the #EuroHPCSummit2023 in Sweden! 🦾 Thank to all of you who visited us at the poster session and who attended session with Mario Kovač (@HPCfer) in organisation with @Etp4HPC 😁
24/03/2023 13:10:00
The summer school addresses young computer science researchers and engineers and is open to outstanding MSc students. Accepted students will spend one week in Barcelona, attending formal lectures, invited talks, and other activities. 🤓
23/03/2023 15:32:00
.@TheOfficialACM Summer School on HPC Computer Architectures for AI and Dedicated Applications, co-hosted by @BSC_CNS and @la_UPC invites you to register until April 15th! ⏰ More about the summer school and registrations here ⬇️
23/03/2023 15:31:00
RT @Etp4HPC: Our 2nd session of the afternoon is starting at #EuroHPCSummit2023 with Mario Kovac from @EuProcessor We're in room 3, join u…
22/03/2023 17:01:00
The #EuroHPCSummit2023 is finally here! 🦾 We look forward to interesting discussions and seeing our colleagues who work on interesting projects. Don't forget to visit us today at the project poster session! 😁
20/03/2023 13:47:00
📣 Join us in the project poster session at #EuroHPCSummit2023! Learn more about our project and our plans for the future. We look forward to seeing you in Sweden in just 4 days! 💪
16/03/2023 12:04:00
Mario Kovač (@HPCfer) will have a keynote speech related to the EPI project today at HPC, Data & Architecture Week in Buenos Aires, Argentina. 🇦🇷 More information about the event here ➡️
13/03/2023 12:31:00
RT @Etp4HPC: 1 week to #EuroHPCSummit2023 ! Don’t miss the 2 sessions run by ETP4HPC on 22 March: 14:30 Emerging Technologies for HPC in Eu…
13/03/2023 10:47:00
The @EuroHPC_JU Summit is approaching! Mario Kovač from @HPCfer will participate in a session "Towards an Autonomous European HPC Supply Chain: Showcasing EuroHPC Projects." EPI will also be present in the poster session. ➡️ See you in Sweden! 🇸🇪
06/03/2023 09:40:00
📢 EPI will be a sponsor of the 2023 edition of @TheOfficialACM Summer School on HPC Computer Architectures for AI and Dedicated Applications, co-hosted by @BSC_CNS and @la_UPC. More about the summer school and registrations here 👇
01/03/2023 14:51:00
RT @hipeac: How is Europe’s quest for a homegrown processor going? We asked Étienne Walter @Atos @EuProcessor #HiPEAC23 #HiPEACTV @EuroHPC…
24/02/2023 14:47:00
RT @Kalrayinc: 📢 Don't miss @Kalrayinc's Keynote at SuperComputing Asia 2023 (#SCA2023)! Benoit Dupont de Dinechin, Kalray's CTO, will tal…
23/02/2023 18:27:00
Étienne Walter (@Atos) spoke to @hipeac about the next steps for the European Processor Initiative. 👀 You can watch the interview here ⬇️
22/02/2023 14:07:00
Manolis Marazakis from @FORTH_ITE had a keynote at the @hipeac conference (RAPIDO workshop) where he presented "Challenges in modelling HPC SoCs: An experience report on using Gem5." More information about the workshop here:
20/01/2023 09:53:00
We would like to thank everyone who participated in our "EPI Tutorial" at the @hipeac conference! 🥳 In addition, we would like to thank our partners @CEA_Officiel, @fzj_jsc, @BSC_CNS and @HPCfer for creating this tutorial💪🏻 #HiPEAC23
18/01/2023 17:10:00
RT @hipeac: 🎸HiPEAC rocks! Day 2 of #HiPEAC23: industry meets academia, students meet former employers. What did you get up to? 👉 https://…
18/01/2023 17:00:00
Today is the last day of the @hipeac conference in Toulouse! Take the opportunity to visit us at booth 14 and learn more about our project. 🦾 #HiPEAC23
18/01/2023 10:18:00
We had a great time at the @hipeac conference yesterday and look forward to today's sessions! 😁 Our team is waiting for you at booth 14 🤓
17/01/2023 10:55:00
RT @fdrcrss: #HiPEAC2023 - Giving a #keynote at @hipeac today at 12:30!
17/01/2023 10:51:00
RT @hipeac: From atoms to applications: find out what we got up to on day 1 of #HiPEAC23, ft. Albert Cohen and Subhasish Mitra 📺 https://t…
17/01/2023 10:50:00
@PCzanik @hipeac Thank you for following and supporting us! We will have an announcement and timeline really soon.
16/01/2023 16:05:00
@PCzanik @hipeac Dear Peter, thank you very much for your question! 😊 We will soon make an announcement regarding your question on the EPI website. In addition, we have an RSS feed where you can follow the project news easier:
16/01/2023 14:19:00
We love to use conferences like #HiPEAC23 to network and meet with our partners and representatives of other initiatives!🦾
16/01/2023 13:54:00
Join us today at @hipeac conference in Toulouse! 💪 You can find us at booth 14, our team looks forward to your questions 😊
16/01/2023 11:11:00
RT @heroes_hpc: Ready for @hipeac 2023 in Toulouse? 🇫🇷 📌Don’t miss our HEROES talk today at 12:00 in the CONCERTO workshop. @HPC_Now partn…
16/01/2023 09:36:00
Save the date for the EPI Tutorial at the @hipeac conference! 🗓️ #HiPEAC23 On Monday you will have the opportunity to participate in a tutorial organised by EPI partners @CEA_Officiel, @fzj_jsc, @BSC_CNS and @fer_unizg! 🦾 More information here ➡️
13/01/2023 12:48:00
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