Next-generation General Purpose Processor (GPP) and Common Platform

The objective of this stream is to move forward with the development of the second-generation EPI microprocessor targeting future European exascale supercomputers by applying technological enhancements to the baseline of GPP Rhea from SGA1.

In parallel, this stream focuses on the development of an open Common Platform standard aiming to efficiently interface processors and accelerators in-package, implementing cache coherency, and validating the toolchains and runtime between processors and accelerators.

Preparing the Next-generation of General Purpose Processor

EPI effort in SGA1 included the definition and design of an HPC Microprocessor targeting V1 Arm cores, HBM, DDR5, PCIeG5/CXL/CCIX. Bringing together partners encompassing academia, research, industrials, system developers and system integrators, the EPI focus was a competitive and performant HPC Processor targeting IP largely from the market, to maximize the probability of first-time success bringing Rhea to market.

In SGA2, SiPearl and Stream 2 partners will increase performance by increasing the number of cores and memory bandwidth, adding in chip acceleration, and custom IP blocks. More specifically, the new generation GPP will uphold word-class competition by:

Addressing key CPU performance metrics including performance per socket, per Watt and per mm2, byte per FLOP ratio, and HPCG efficiency (i.e., the ratio between the HPCG performance and the peak performance)
Increasing the memory bandwidth
Implementing the latest interconnects such as CXL
Improving energy efficiency on key applications by updating the silicon process and the micro-architecture
Improving package integration through D2D interface driven by the common platform activities
Enforcing security with elements such as memory and link encryption, post-quantum cryptography
Preparing compliance readiness for CC EAL4+ certification
Offering a rich software ecosystem supporting the objectives of a software common platform.

Stream 2 will validate performance based on prototype boards that will be the basis for general-purpose compute nodes in large scale HPC systems.

Common Platform

In EPI SGA2, work on the “Common Platform” (common to the GPP & Accelerator streams) will be further developed at hardware and software levels in continuation of EPI SGA1.

Stream 2 will produce the specification that defines the hardware Common Platform for the chip and system integrating technologies to address the need for designing decoupled systems combining hybrid compute units, with closely coupled performance and ease of use.

Use cases will be studied to specify requirements for the hardware Common Platform Architectural specification. As part of these activities, interfaces such as the latest CXL, CCIX, and PCIe will be considered. Specifically, CXL will offer memory and I/O coherency, lower latency than PCIe and future proofing. Moreover, we will analyse die-to-die interfaces for chiplet-chiplet interconnects: BOW, UCIe, and XSR are some of the candidate solutions to be analysed for performance as well as expected industry acceptance and availability.

From a software perspective, the objectives of the Common Platform are to elaborate an ecosystem and a set of methods and tools to program accelerators seamlessly across socket-socket or die-to-die interfaces. This will be achieved by selecting or developing standards for connections between heterogeneous elements including software support for physical interconnects, SW orchestration, and support for memory coherency. This will enable the development of generic programming approaches that ensure code portability and performance portability, and ultimately aid performance testing on HPC platforms offering different processor technologies.

The expected achievements consist in aligning with, modifying, or building a standard for hardware Common Platform implementing the software flow to offload computing tasks to accelerator units and the related accelerator software flow.

Validation and Codesign

Stream 1 will bring up EPI’s first generation processor (Rhea 1) and board, then connect the EPI accelerator (EPAC v1.0/1.5) to the board via PCIe to build a hardware prototype on which software will be installed and applications ported. This will serve to validate the first generation of European processors targeted for the HPC market.

Simultaneously, a co-design process will take place targeting the second EPI generations (Rhea-2 and EPAC v2) chips to be developed in EPI. Application requirements will be collected and simulation-based architecture analysis performed to identify the best suited design parameters.

Codesign

In EPI, processor development is driven by co-design, which is understood as a bi-directional and iterative interaction process between application owners, hardware, and system-software developers from Streams 2 and 3. The EPI benchmark suite, constituted by a wide variety of applications, mini-apps and synthetic benchmarks, is the basis for the characterization of the application-requirements. Quantitative user-requirements are determined running various elements of the benchmark suite on reference platforms, simulators, modelling tools, and emulation hardware. With these, the impact of specific design parameters into application’s performance, energy efficiency, and resiliency are studied. The benefits of given microarchitecture features in terms of time-to-solution and energy-to-solution are evaluated against cost-related considerations such as area or component price, and trade-off analysis are performed to find sweet spots where the chip design is frozen. The evaluation of Rhea and EPAC v1.0 will also provide valuable insight on the features that might need to be improved in the second-generation EPI products.

Bringup, Prototyping and Validation

State of the art techniques will be used to bring to life the Rhea processor and the Rhea reference board (Rhea REF) manufactured by Atos. A validation plan will be employed and updated to ensure the good quality of the products, and, if necessary, a new board revision will be triggered to fix all detected issues.

Once the functionality of the boards is verified, they will be integrated into engineering prototypes, on which low-level tests are run to verify its operation and stability, to then assemble them into a small-size cluster. The Rhea cluster, in which power distribution, cooling infrastructure, and sensors for safe operation are key elements, will be manufactured by E4 Computer Engineering and operated at their premises. It will contain up to 8 Rhea-REF boards, some of them hosting a PCIe-attached EPAC v1.0/v1.5 Daughter Board, to develop and test a GPP + ACCELERATOR environment. In parallel, a mini-cluster interconnecting up to 3 EPAC v1.0 accelerators will be assembled at BSC, and later upgraded to EPAC v1.5.

Remote access to the Rhea and EPAC clusters will be given to the validation team, once the complete compute software stack (from OS to programming environment and libraries) is installed on the systems. The validation team will use the EPI benchmark suite to run first small benchmarks on the prototype clusters, then mini-apps, and end up with full application codes. These tests will serve as stress tests for the clusters, informing also about their functionality, performance, ease of use, and reliability. In summary, these application runs will deliver the ultimate validation of the Rhea and EPAC v1.0/1.5 products, indicating whether they are ready for general deployment and qualified to build a large-scale HPC system.

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