The European Processor Initiative Co-Design Workshop, held on September 10-11 at FORTH (Heraklion, Greece), brought together leading Centres of Excellence (CoEs), research institutions, HPC companies, and hardware/software experts to advance Europe’s sovereignty in high-performance computing through collaborative hardware/software co-design. The workshop sessions showcased progress in adapting flagship scientific applications to emerging European processor technologies (with the Arm and RISC-V ISAs), integration of advanced memory hierarchies, and leveraging novel architectures such as chiplets and interposers. The workshop sessions, moderated by Etienne Walter (Eviden) and Manolis Marazakis (FORTH), included 2 keynotes, 20 technical presentations, and 2 panels.
Keynotes
Jesus Labarta (BSC), in his keynote on September 10 (Day-1), examined GPU-AI co-design through an HPC lens, emphasizing the value of combining microscopic-level analysis of computational kernel behavior together with macroscopic metrics for deep insights into performance. This approach is at the heart of tool-assisted co-design, and was showcased with the use of trace capture and analysis/visualization tools to reveal bottlenecks in large-scale AI workloads with the aim to guide RISC-V vectorization architectural optimizations.
Denis Dutoit (CEA-LETI), in his keynote on September 11 (Day-2), surveyed chiplet and interposer technology, highlighting their role in building complex systems through architectural disaggregation and packaging aggregation. Chiplets/interposers address energy-efficiency and scaling limits in HPC/embedded systems, and offer Europe a strategic opportunity to enhance computing autonomy via modular integration and a distributed supply chain.
Presentations of Day-1
Experiences and learnings from the EPAC test-chip were presented by Filippo Mantovani (BSC). The EPAC test-chip pairs a RISC-V scalar core with a long-vector VPU (supporting up to 16k-bit registers) for HPC efficiency. Hardware design tradeoffs have enabled high-throughput vector processing via multi-cycle execution. Co-design across compilers, libraries, and programming models (incl. auto-vectorization, pragmas, intrinsics) has been crucial for practical deployment.
The roadmap of the Rhea family of processors by SiPearl was presented by Craig Prunty (SiPearl). SiPearl advances European compute sovereignty by developing highly complex, energy-efficient Arm-based processors for HPC and AI. SiPearl positions its technology, exemplified by the upcoming deployment of Rhea processors in the JUPITER exascale system, as a key enabler for achieving high performance with superior energy efficiency.
RISC-V IP for bandwidth-intensive SoCs was presented by Jose-Maria Arnau (Semidynamics). Key innovations include “Gazzillion Misses” technology to mitigate memory latency and maximize bandwidth utilization, and tightly integrated out-of-order CPU cores with configurable Vector/Tensor Units for demanding AI and HPC workloads.
Experiences and perspectives from the EUPILOT project were presented by Carlos Puchol (BSC). The EUPILOT project aims to build a European accelerator platform using RISC-V technology to enhance HPC/AI supply-chain autonomy. Key innovations include modular hardware (EAM) with liquid-immersion cooling for energy efficiency, and extensive software porting/optimization for scientific workloads.
Codesign experiences in the EUPEX project were presented by Matteo Turisini (CINECA). The EUPEX project advances a European modular exascale supercomputer using ARM-based processors and software tools, prioritizing co-design with scientific applications. A primary focus in EUPEX has been the enablement of energy-efficient workflows via comprehensive toolchains.
RAS (Reliability, Availability, Serviceability) concerns were addressed in two presentations. Dimitris Gizopoulos (University of Athens) discussed Silent Data Corruptions (SDCs): unnoticed hardware faults causing incorrect outputs. SDCs are a critical reliability risk in large-scale computing. Even low per-CPU SDC rates (0.3–1 per 1000) translate to significant corrupted results at hyperscaler scale. Addressing SDCs requires a co-design approach across hardware and systems, following the pattern: Model, Measure, Detect, Mitigate.
Daniele Rossi (University of Pisa) described ENGAGE-V, a modular and RERI-compliant RAS IP for RISC-V systems, applicable across diverse application domains. Standardized error logging and reporting IP is crucial beyond just detection/correction (e.g. via ECC) to improve serviceability and availability. ENGAGE-V provides a flexible, lightweight solution for capturing error context and triggering targeted software recovery, complementing existing techniques.
Presentations of Day-2
Two presentations provided perspectives on Arm and GPU technologies, offering a view of the historical evolution from low-power ARM+GPU platforms to modern high-performance HPC accelerators, with attention to power envelopes and heterogeneous integration. Jean-Pierre Panzierra (Eviden & ETP4HPC) provided a personal account detailing Europe’s 15-year journey (2010–2025) to establish an Arm-based HPC ecosystem, driven by sovereignty concerns. Persistent collaboration across research (incl. the MontBlanc series of projects) and industry was essential to overcome hardware/software gaps. Despite vendor and market unpredictability, viable Arm HPC servers has been achieved through iterative refinement.
Filippo Spiga (NVIDIA) traced the evolution of Arm processors and GPU acceleration in HPC. Early prototypes like CARMA (2012) demonstrated the energy efficiency of Arm+GPU designs, paving the way for modern datacenter solutions. Industry momentum (e.g., Arm Neoverse, NVIDIA Grace) and software ecosystems (CUDA, Jetson) now enable co-designed, power-efficient HPC systems.
Paul Carpenter (BSC) presented an overview of the Digital Autonomy with RISC-V in Europe (DARE) project. The DARE project advances European HPC/AI sovereignty through a RISC‑V‑centric open stack, combining chiplet-based hardware (vector, AI, and general-purpose processors) and full software co-design. Key goals include energy-efficient exascale-ready silicon, AI-accelerated workloads, and prototypes enabling next-generation scientific computing. Among other innovations, DARE encompasses in-memory computing accelerators for robust AI and virtual/physical prototyping for rapid system validation.
Matteo Mascagni (EuroHPC JU) provided a personal interpretation of co-design, emphasizing upcoming daunting energy efficiency and sustainability challenges (especially for zettascale systems). He argued that current HPC practices often mislabel software tuning for off-the-shelf hardware as true “Hardware/Software Co-Design”, which instead requires coordinated development of both types of components. Sustainable zettascale demands true co-design, i.e. application-driven hardware/software collaboration prioritizing energy efficiency, heterogeneity, and data locality. Critical shifts include moving beyond CPU-centric models to accelerator-dominated architectures, mixed-precision computing, and Gustafson’s Law scalability.
Lluc Alvarez (BSC) presented an overview of the Barcelona Zettascale Lab project, which focuses on open RISC-V hardware co-design, targeting a high-performance multicore processor and vector accelerator. Key achievements include planned Intel Foundry tapeouts, a 150+ multidisciplinary team, and contributions to EU initiatives like EPI.
Vassilis Papaefstahiou (FORTH) presented a retrospective on the evolution of RISC‑V EPI prototypes, with emphasis on the memory hierarchy and tiled architecture, and highlighting two central design decisions: (1) Adoption of AMBA5 CHI coherence with distributed non-blocking L2/LLC slices for high-bandwidth vector/ML workloads and (2) Strategic use of FPGA bridging via C2C links for early validation and I/O, enabling practical silicon bring-up across multiple tape-outs.
Mario Kovač (University of Zagreb) presented FAUST, a highly configurable FPU for RISC-V vector processors, compliant with IEEE 754-2019 and RVV v1.0. Key features include extensive operation support (FMA, division, conversions) and flexible pipeline tuning. FAUST 2.0 significantly reduces area through manual register placement and algorithm choices while maintaining performance and standards compliance.
Sylvie Lesmanne (Eviden) and Denis Dutoit (CEA-LETI), with contributions by Anthony Philippe (CEA-LETI) and Romain Dolbeau (SiPearl), presented the EPI Common Platform, a system architecture blueprint for processors and accelerators that prioritizes vendor neutrality and performance efficiency. The EPI Common Platform relies on two pillars: (1) A software platform leveraging open standards (MPI, OpenMP, SYCL) to enable portable hybrid programming across diverse hardware, and (2) A hardware platform adopting chiplet-based designs and global D2D standards (specifically UCIe) for scalable, interoperable systems.
Panels
The panel on Day-1 examined technology challenges and opportunities for European chips. Starting from the technical points raised during the presentation of the EPI Common Platform, the panel also considered challenges due to the organizational complexity of large-scale projects and the difficulty in establishing trust in a market context. Other challenges discussed include access to the latest EDA tools, and access to funding in relatively short timeframes. The concept of mission-specific HPC was also discussed, as a co-design path distinct of general-purpose computing, as a way to address power consumption and cooling challenges at extreme scales.
The theme of the panel on Day-2 was how to apply codesign to meet future needs of the European HPC ecosystem. Five ongoing CoEs presented summaries of their work in adapting and optimizing domain-specific codes for exascale systems.
Plasma-PEPSC focuses on flagship plasma simulation codes (BIT1, GENE, PIConGPU, Vlasiator) for fusion energy, plasma accelerators, and space physics. Optimization strategies include SVE/NEON vectorization, cache locality improvements, and precision reduction, tested on Arm-based Rhea platforms.
SPACE develops scalable astrophysical simulation codes, assessing ARM readiness, SIMD vectorization impacts, energy tuning, and HBM relevancy for performance gains.
MaX3 targets materials science applications (Quantum ESPRESSO, Yambo, BigDFT, FLEUR, Siesta) with studies on HBM vs DDR performance, fine-grained object-level HBM placement, and vectorization improvements across architectures.
ESiWACE3 focuses on Weather and climate simulation workloads explored on ARM and RISC-V platforms, demonstrating RVV-based vectorization on real hardware and highlighting ARM maturity and potential for RISC-V in HPC.
ChEESE2P models solid earth phenomena (seismic waves, volcanology, tsunami) using mini-apps to study ARM+HBM and RISC-V accelerator integration, emphasizing memory bandwidth’s critical role.
Conclusion
Overall, the workshop provided a comprehensive overview of how the European Processor Initiative is contributing to create a sustainable and sovereign European HPC ecosystem, by co-developing processors, accelerators, and software stacks tailored to the needs of strategic scientific domains. Through iterative co-design cycles, domain specialists and hardware designers work together to realize exascale-ready applications, ensuring that Europe remains competitive in global HPC innovation and maintains control over critical computational technologies.
Materials are available in our dissemination and communication repository: https://www.european-processor-initiative.eu/dissemination-material/codesign-workshop-in-heraklion/
