Home Dissemination Communication Press Repository VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library

VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library

EPI Consortium members published “VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library” in IEEE Access.

Here is a link to an open-access version of the article: https://ieeexplore.ieee.org/document/10182260

DOI: https://doi.org/10.1109/ACCESS.2023.3295245

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Publication Type: Journal Article
Year of Publication: 2023
Authors: Matteo Lo Gerfo - Sergio Saponara - Stefano Di Matteo
Publisher: IEEE Access
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Keywords:
URL: https://ieeexplore.ieee.org/document/10182260

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This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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