Home Dissemination Communication Press Repository Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

EPI Consortium members published “Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing” in IEEE Micro.

Here you can find a link to an open access version of the article:

https://arxiv.org/abs/2008.06502

DOI: https://doi.org/10.1109/MM.2020.3045564

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Publication Type: Journal Article
Year of Publication: 2020
Authors: Fabian Schuiki - Florian Zaruba - Luca Benini
Publisher: IEEE
Name of publication/Event:
ISSN Number: Electronic ISSN: 1937-4143
Keywords: FPU, RISC-V
URL:

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This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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