From January 20 to 23, HiPEAC25 took place Palau de Congressos de Barcelona in Barcelona, Spain. Our team from BSC and FORTH was at the booth #21, answering questions about the road so far in the European Processor Initiative and showcasing EPAC – European Processor Accelerator demo.

In addition to that, colleagues from E4 Computer Engineering SpA and Barcelona Supercomputing Center organized a workshop titled “RISC-V: the cornerstone ISA for the next generation of HPC infrastructures”. There, our colleague from BSC, Pablo Vizcaino, presented his paper titled “RAVE: The RISC-V Analyzer of Vector Executions”.

Alexandra Kourfali from EuroHPC Joint Undertaking (EuroHPC JU) gave an overview of EuroHPC RISC-V initiatives.

Marta Garcia-Gasulla from BSC also attended a workshop organized by Centers of Excellence, where she gave a talk titled “Co-design, from a buzzword to a reality, an EPI success story”. She explained a very high overview of the different architectures being developed at EPI, an explanation of what the SDVs (Software Development Vehicles) are and how they can be used to co-design applications, system software and hardware. She also talked about the success story of a collaboration between EPI and the CEEC Center of Excellence, where she and her colleagues optimized a CFD code for the EPAC accelerator using the SDVs.

Marta Garcia-Gasulla at HiPEAC workshop

The presentations are available here, in our dissemination repository.