The European Processor Initiative held a codesign workshop on September 10 and 11, in Heraklion, Greece.
This two-day workshop brought together leading researchers and industry experts to explore the future of high-performance computing in Europe. Key topics included performance analysis with EPAC, next-generation chip architectures (Arm, RISC-V), chiplet technologies, and reliability challenges. The program featured keynotes on energy-efficient computing and exascale systems, alongside project experiences from projects closely collaborating with EPI (including EUPEX, EUPILOT, and DARE).
Presentations are available in the .zip file of this item.
At HiPEAC25, EPI colleagues from BSC had two presentations:
Pablo Vizcaino: RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin
Marta Garcia-Gasulla: Co-design, from a buzzword to a reality, an EPI success story
Find them here in the ZIP attached.
EPI held its first EPI forum in Barcelona, on October 9 and 10, 2024. It was a two-day event with the following presentations:
The presentations are available in the zip file of this item.
Presentations from partners who participated in this year’s HiPEAC conference in Toulouse, France.
Klas Moreau from ZeroPoint Technologies had a presentation at SEDEX 2022.
Filippo Mantovani from BSC held a presentation at CECAM 2022.
Daniele Cesarini held a presentation at REHE 2022.
Jesús Labarta and Roger Ferrer Ibáñez held presentations at 2022 ACM Europe Summer School.
Roger Espasa (Semidynamics) held a presentation at HiPEAC 2022 Conference in Budapest.
Joao Mario Domingos, Nuno Neves, Nuno Roma and Pedro Tomás held a poster presentation titled “Unlimited Vector Extension with Data Streaming Support.”