EPI Consortium members published “Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study” at ISC High Performance 2023: High Performance Computing.
Here you can find a link to an open access version of the article: https://arxiv.org/abs/2306.01797
DOI: https://doi.org/10.1007/978-3-031-40843-4_39
Presentation from the conference is also available below in .pdf.
Europe to Dish out €270 Million to Build RISC-V Hardware and Software
RISC-V Is Far from Being an Alternative to x86 and Arm in HPC
EPI Consortium members published “NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator” in IEEE Transactions on Circuits and Systems I: Regular Papers.
Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9763876.
DOI: https://doi.org/10.1109/TCSI.2022.3166550.
Roger Espasa (Semidynamics) held a presentation at HiPEAC 2022 Conference in Budapest.
John D. Davis from BSC held a talk titled “RISC-V in Europe: The Road to an Open Source HPC Stack.”
Jesús Labarta (BSC) held a presentation titled “RISC-V vector processor in EPI (European Processor Initiative).”
Francesco Minervini and Oscar Palomar Perez from BSC presented the RISC-V vector accelerator at RISC-V Summit 2021. Their talk was titled Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing.
E4 Announces the RISC-V-Based Monte Cimone Cluster
Roger Espasa from Semidynamics held a presentation titled “OVI: The Open Vector Interface.”
