RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

EPI Consortium members published “NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator” in IEEE Transactions on Circuits and Systems I: Regular Papers.

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9763876.

DOI: https://doi.org/10.1109/TCSI.2022.3166550.

Roger Espasa (Semidynamics) held a presentation at HiPEAC 2022 Conference in Budapest.

John D. Davis from BSC held a talk titled “RISC-V in Europe: The Road to an Open Source HPC Stack.”

Jesús Labarta (BSC) held a presentation titled “RISC-V vector processor in EPI (European Processor Initiative).”

Francesco Minervini and Oscar Palomar Perez from BSC presented the RISC-V vector accelerator at RISC-V Summit 2021. Their talk was titled Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing.  

E4 Announces the RISC-V-Based Monte Cimone Cluster

Roger Espasa from Semidynamics held a presentation titled “OVI: The Open Vector Interface.”

EPI Consortium members published “A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications” in IEEE Transactions on Emerging Topics in Computing.

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9583876.

DOI: https://doi.ieeecomputersociety.org/10.1109/TETC.2021.3120538.

Jesus Labarta held a presentation titled “Performance analysis and hybrid programming in HPC”, Mauro Olivieri held a presentation “Vector acceleration in HPC and Edge Devices” and Roger Espasa held a presentation “Avispado: A RISC-V core supporting the RISC-V vector instruction set.”

 

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