The European Processor Initiative held a codesign workshop on September 10 and 11, in Heraklion, Greece.

This two-day workshop brought together leading researchers and industry experts to explore the future of high-performance computing in Europe. Key topics included performance analysis with EPAC, next-generation chip architectures (Arm, RISC-V), chiplet technologies, and reliability challenges. The program featured keynotes on energy-efficient computing and exascale systems, alongside project experiences from projects closely collaborating with EPI (including EUPEX, EUPILOT, and DARE).

Presentations are available in the .zip file of this item.

At HiPEAC25, EPI colleagues from BSC had two presentations:

Pablo Vizcaino: RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin

Marta Garcia-Gasulla: Co-design, from a buzzword to a reality, an EPI success story

Find them here in the ZIP attached.

The European Processor Initiative aims to bring together research, design and manufacturing of a home-grown European processor

EPI held its first EPI forum in Barcelona, on October 9 and 10, 2024. It was a two-day event with the following presentations:

• Etienne Walter (Eviden, an Atos business): EPI Overview
• Stephane Requena (GENCI): AI Keynote
• Mateo Valero (BSC): European Supercomputers Keynote: Buy versus Build
• Jean-Pierre Panziera (Eviden, an Atos business): High Performance Computing in the AI era
• Eric Lalardie (Arm): Enabling European Innovation with Arm Technology
• Daniele Piccarozzi (AMD): AMD solutions for HPC and AI
• Philippe Notton (SiPearl): Overview of SiPearl’s Seine Platform
• Roger Espasa (SMD): Semidynamics All-in-One solution for next-generation RISC-V AI
• Craig Prunty (SiPearl): Arm/Rhea in high-end HPC
• Alexandra Kourfali (EuroHPC JU): EuroHPC chips initiatives: the road towards European technological sovereignty
• Rod Evans (NVIDIA): Enabling AI Nations
• Filippo Mantovani (BSC): Pushing RISC-V to HPC: the story of EPI Accelerator (EPAC)
• Filippo Mantovani (BSC): VEC
• Andrea Bocco (CEA): VRP
• Tim Fischer (ETHZ): STX
• David Snelling (Fujitsu): Fujitsu-Monaka: Data Center Ready, ARM Processor

The presentations are available in the zip file of this item.

Europe to Dish out €270 Million to Build RISC-V Hardware and Software

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

EPI Consortium members published “NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator” in IEEE Transactions on Circuits and Systems I: Regular Papers.

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9763876.

DOI: https://doi.org/10.1109/TCSI.2022.3166550.

Roger Espasa (Semidynamics) held a presentation at HiPEAC 2022 Conference in Budapest.

John D. Davis from BSC held a talk titled “RISC-V in Europe: The Road to an Open Source HPC Stack.”