At HiPEAC25, EPI colleagues from BSC had two presentations:
Pablo Vizcaino: RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin
Marta Garcia-Gasulla: Co-design, from a buzzword to a reality, an EPI success story
Find them here in the ZIP attached.
EPI held its first EPI forum in Barcelona, on October 9 and 10, 2024. It was a two-day event with the following presentations:
- Etienne Walter (Eviden, an Atos business): EPI Overview
- Stephane Requena (GENCI): AI Keynote
- Mateo Valero (BSC): European Supercomputers Keynote: Buy versus Build
- Jean-Pierre Panziera (Eviden, an Atos business): High Performance Computing in the AI era
- Eric Lalardie (Arm): Enabling European Innovation with Arm Technology
- Daniele Piccarozzi (AMD): AMD solutions for HPC and AI
- Philippe Notton (SiPearl): Overview of SiPearl’s Seine Platform
- Roger Espasa (SMD): Semidynamics All-in-One solution for next-generation RISC-V AI
- Craig Prunty (SiPearl): Arm/Rhea in high-end HPC
- Alexandra Kourfali (EuroHPC JU): EuroHPC chips initiatives: the road towards European technological sovereignty
- Rod Evans (NVIDIA): Enabling AI Nations
- Filippo Mantovani (BSC): Pushing RISC-V to HPC: the story of EPI Accelerator (EPAC)
- Filippo Mantovani (BSC): VEC
- Andrea Bocco (CEA): VRP
- Tim Fischer (ETHZ): STX
- David Snelling (Fujitsu): Fujitsu-Monaka: Data Center Ready, ARM Processor
The presentations are available in the zip file of this item.
Chairman of EPI Board, Jean-Marc Denis, held a keynote at HPC Asia 2021.
EPI team participated in several activities in Digital HiPEAC 2021 conference: EPI Tutorial, Industrial session, and WRC workshop.
The materials are all zipped here, and a link to YT recording of the Tutorial is available.
EPI consortium members participated in the HPC CoE meeting and gave presentations to the CoE members.
Here you can find the presentation on Co-design.
