EPI Consortium members published “FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit” in Microprocessors and Microsystems Journal.

Here is a link to an open-access version of the article: https://www.sciencedirect.com/science/article/abs/pii/S014193312300008X

DOI: https://doi.org/10.1016/j.micpro.2023.104762

EPI Consortium members published “Reusable Verification Environment for a RISC-V Vector Accelerator” in DVCON – Design and Verification Conference Europe Proceedings.

Here is a link to an open-access version of the article: https://dvcon-proceedings.org/document/reusable-verification-environment-for-a-risc-v-vector-accelerator/ .

URI: http://hdl.handle.net/2117/386166

EPI Consortium members published “Functional verification of a RISC-V vector accelerator” in IEEE Design & Test.

Here is a link to an open-access version of the article: https://upcommons.upc.edu/handle/2117/382717.

DOI: 10.1109/MDAT.2022.3226709.

EPI Consortium members published “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” in ACM Transactions on Architecture and Code Optimization.

Here is a link to an open-access version of the article: https://dl.acm.org/doi/10.1145/3575861.

DOI: https://doi.org/10.1145/3575861.

Francesco Minervini and Oscar Palomar Perez from BSC presented the RISC-V vector accelerator at RISC-V Summit 2021. Their talk was titled Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing.  

Oscar Palomar from BSC presented energy-efficient vector architectures at the LEGaTO project workshop. Slides can be accessed here: https://www.slideshare.net/secret/hUCxifkvkFVyic