EPI Consortium members published “FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit” in Microprocessors and Microsystems Journal.

Here is a link to an open-access version of the article: https://www.sciencedirect.com/science/article/abs/pii/S014193312300008X

DOI: https://doi.org/10.1016/j.micpro.2023.104762

EPI Consortium members published “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” in ACM Transactions on Architecture and Code Optimization.

Here is a link to an open-access version of the article: https://dl.acm.org/doi/10.1145/3575861.

DOI: https://doi.org/10.1145/3575861.

Francesco Minervini from BSC held a presentation titled: “Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing” at Spring 2022 RISC-V Week.

Francesco Minervini and Oscar Palomar Perez from BSC presented the RISC-V vector accelerator at RISC-V Summit 2021. Their talk was titled Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing.