EPI Consortium members published “Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA” in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
Here is a link to an open-access version of the article: https://ieeexplore.ieee.org/document/9912073/authors#authors.
EPI Consortium members published “Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs” at the DATE 2022 Conference.
Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9774716.
This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.