EPI team participated in several activities in Digital HiPEAC 2021 conference: EPI Tutorial, Industrial session, and WRC workshop.

The materials are all zipped here, and a link to YT recording of the Tutorial is available.

EPI team members participated in several sessions at the HiPEAC conference in Bologna, Italy, held from January 20-22, 2020.

In addition to having a booth as a HiPEAC sponsor, EPI was presented at the industrial session, in two other workshops (WRC and Eurolab4HPC session) and in EPI’s own tutorial session, where EPI presenters gave talks on Accelerators, Compiler and Software Development, EPI’s Power Aspect and PCIe Daughter.

At the 2nd RISC-V Meetings, organized by IRT Nanoelec and CEA and The Scientific Day of IRT SE & GDR SOC2: RISC-V for critical embedded systems, organized by IRT St-Exupéry and GDR SOC2, EPI partners held two presentations.

The first one made by Romain Dolbeau, who gave a talk titled “European Processor Initiative: challenges & opportunities for RISC-V accelerators in an HPC platform”, is available upon request due to file size. The second, done by Denis Dutoit, is available for download here. Ater an introduction on High Performance Computing new challenges and associated technology/architecture evolution, the presentation highlighted the EPI position statement on generic computing, accelerator with RISC-V and design methodology. The presentation concluded with an explanation of EPI’s roadmap towards a wide range of applications from Exascale computing to embedded HPC.

EPI First tutorial called “First steps towards a made-in-Europe high-performance microprocessor” was held on July 17th, at the Universita Politècnica de Catalunya, co-located with the ACM 2019 Summer school on HPC architectures for AI and dedicated applications. Andrea Bartolini presented the introductory section, covering several aspects of the HPC processor landscape.

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