EPI Consortium members published “RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator” in 2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST).

DOI: https://doi.org/10.1109/MOCAST61810.2024.10615493

EPI Consortium members published “HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement” in the IEEE Access.

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10508585

DOI: https://doi.org/10.1109/ACCESS.2024.3393844

EPI Consortium members published “Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures” at SEEDA-CECNSM.

DOI: https://doi.org./10.1109/SEEDA-CECNSM61561.2023.10470707

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This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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