EPI Consortium members published “Reusable Verification Environment for a RISC-V Vector Accelerator” in DVCON – Design and Verification Conference Europe Proceedings.
Here is a link to an open-access version of the article: https://dvcon-proceedings.org/document/reusable-verification-environment-for-a-risc-v-vector-accelerator/ .
URI: http://hdl.handle.net/2117/386166
JUPITER Exascale Supercomputer, lead customer for SiPearl
Project press release, published on November 8th, 2023, is also available in the news section: https://www.european-processor-initiative.eu/european-processor-initiative-announces-the-successful-bring-up-of-the-epac1-5-acceleration-chip/
Project press release, published on November 6th, 2023, is also available in the news section: https://www.european-processor-initiative.eu/epi-partner-sipearl-will-provide-its-general-purpose-processor-for-europes-first-eurohpc-exascale-supercomputer-jupiter/ .
SiPearl has raised €90m in financing which will allow the commercialisation of Rhea
The project’s Yearly Public Report, Deliverable D28.3, is available here.
EPI Consortium members published “Functional verification of a RISC-V vector accelerator” in IEEE Design & Test.
Here is a link to an open-access version of the article: https://upcommons.upc.edu/handle/2117/382717.
DOI: 10.1109/MDAT.2022.3226709.
EPI Consortium members published “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” in ACM Transactions on Architecture and Code Optimization.
Here is a link to an open-access version of the article: https://dl.acm.org/doi/10.1145/3575861.
DOI: https://doi.org/10.1145/3575861.
EPI Consortium members published “gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM” in 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
Here is a link to an open-access version of the article: https://ieeexplore.ieee.org/document/9980925/authors#authors.
DOI: 10.1109/SBAC-PAD55451.2022.00015.
EPI Consortium members published “Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA” in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
Here is a link to an open-access version of the article: https://ieeexplore.ieee.org/document/9912073/authors#authors.