The European Processor Initiative held a codesign workshop on September 10 and 11, in Heraklion, Greece.
This two-day workshop brought together leading researchers and industry experts to explore the future of high-performance computing in Europe. Key topics included performance analysis with EPAC, next-generation chip architectures (Arm, RISC-V), chiplet technologies, and reliability challenges. The program featured keynotes on energy-efficient computing and exascale systems, alongside project experiences from projects closely collaborating with EPI (including EUPEX, EUPILOT, and DARE).
Presentations are available in the .zip file of this item.
Project press release, published on September 18th, 2025, is also available in the news section:
EPI Consortium members published “A Mess of Memory System Benchmarking, Simulation and Application Profiling” in 22024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO).
Here you can find a link to an open access version of the article: https://arxiv.org/pdf/2405.10170
European Funding Deals: SiPearl, Exein, Q.Ant Aim For Scaleup
SiPearl Tapes Out Rhea1 Processor, Closes Series A, Preps Series B
With Money And Rhea1 Tapeout, SiPearl Gets Real About HPC CPUs
SiPearl ships reference node design for Rhea1 high-spec Arm chip
Semiconductors at the Heart of Europe’s Push for Technological Sovereignty
Smarter memory paves the way for EU independence in computer manufacturing
At HiPEAC25, EPI colleagues from BSC had two presentations:
Pablo Vizcaino: RAVE: RISC-V Analyzer of Vector Executions, a QEMU tracing plugin
Marta Garcia-Gasulla: Co-design, from a buzzword to a reality, an EPI success story
Find them here in the ZIP attached.
