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EPI Forum
Pre-register now: 16-17 March 2020, Paris

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EPI Forum 2020

The European Processor Initiative is organising its first EPI Forum on March 16 and 17, 2020, in Paris, France.

EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative.

In order to register your interest to attend the Forum, we invite you to please fill out the form at https://www.european-processor-initiative.eu/forum-preregistration/ and you will be contacted by the Organizing committee of the Forum shortly. Our privacy policy with respect to your data is available here: https://www.european-processor-initiative.eu/privacy-policy-data-privacy-notice/

The venue of the Forum is Elysées Biarritz, 22-24 Rue Quentin-Bauchart, 75008 Paris, France. The final registration price is 250 EUR, while the Draft of the two-day event agenda is available here: EPI Forum Agenda Draft

Upon completing the pre-registration, you will be contacted by the Organizing comittee with further details for registration and payment.

The Organizing comittee reserves the right to implement changes to the Agenda. Should you have any inquiries related to the EPI Forum, please contact us at epi-forum [at] european-processor-initiative.eu

EPI Forum Speakers

Thomas Skordas European Commission, DG CONNECT

Thomas Skordas received his diploma in Electrical Engineering in 1984 and a PhD in Computer Science in 1988. From 1988 to 1995, he worked in France as a Research Fellow and project leader in EU-funded R&D projects in the areas of Information Technology and Robotics.

In 1995, Thomas joined the European Commission as a Research Programme Officer in the Directorate General Information Society & Media (DG INFSO).  Ever since, Thomas worked in various units of DG INFSO (which, in 2012 became DG CONNECT) dealing with ICT research in the context of EU’s Research and Innovation Framework Programmes. From 2006 to 2009, he was Deputy Head of Unit in ICT Security and Trust. In 2009, he was appointed Head of the Photonics Unit and in 2014, Head of the Flagships Unit.

Since March 2017, Thomas is the Director of DG Connect’s “Digital Excellence and Science Infrastructure Directorate”.

Brent Gorda Arm, Inc.

Brent Gorda is the Senior HPC Executive for Arm, Inc. His responsibilities cover the world-wide business opportunities and evangelism in support of the Arm ecosystem. Brent has a history of disruptive change in High Performance Computing. Originally from Canada, Brent started as a compiler writer for parallel computing in the late 1980s. Much of his career has been with the US Department of Energy National Labs at Livermore and Berkeley. He was deeply involved in the transition from large vector systems to the parallel computing paradigm we have today, as well as the BlueGene architecture. An entrepreneur at heart, Brent co-founded Software Carpentry, (http://softwarecarpentry.org), originated the Student Cluster Competition (https://www.studentclustercompetition.us/) and was founder & CEO of Whamcloud, the company that kept Lustre in play for HPC (www.Whamcloud.com). After selling Whamcloud to Intel, Brent ran the High-Performance Data Division for several years.  Now at Arm, Brent is excited to help usher in the next generation of architectural choice for HPC, Cloud & Server computing.

Steve Scott Hewlett Packard Enterprise

Steve Scott is Senior Vice President, Senior Fellow, and Chief Technology Officer of HPC and AI at Hewlett Packard Enterprise, where he is responsible for guiding the long-term technical direction of computing, storage and analytics/AI products within the HPC & AI Business Unit.  Steve holds 42 US patents, and was the chief architect of several supercomputers and interconnects at Cray, which was acquired by HPE in 2019. He received the 2005 ACM Maurice Wilkes Award and the 2005 IEEE Seymour Cray Computer Engineering Award, and is a Fellow of the ACM and the IEEE.  Steve earned a BS in electrical and computer engineering, and a Masters and PhD in computer architecture, all from the University of Wisconsin Madison.

Paul de Bot TSMC Europe BV

Paul de Bot is Senior Director Emerging Business of TSMC Europe BV.

Starting his career in the area of video technology, Paul reached the position of Chief Strategy Officer of Philips Digital Networks.

In 2003 he joined Philips Semiconductors (later NXP Semiconductors) as Vice President Strategy & Business Development for their consumer, automotive and identification businesses, respectively.

Before joining TSMC, Paul had executive roles in the software industry and in corporate finance.

Paul holds MSc degrees in Electrical Engineering and Corporate Finance and a Professional Doctorate in Engineering.

Mitsuhisa Sato RIKEN Center for Computational Science

Mitsuhisa Sato is a deputy Director of RIKEN Center for Computational Science since 2018. He received the M.S. degree and the Ph.D. degree in information science from the University of Tokyo in 1984 and 1990.

From 2001, he was a professor of Graduate School of Systems and Information Engineering, University of Tsukuba. He has been working as a director of Center for computational sciences, University of Tsukuba from 2007 to 2013. Since October 2010, he is appointed to the research team leader of programming environment research team in Advanced Institute of Computational Science (AICS), renamed to R-CCS, RIKEN.

Since 2014, he is working as a team leader of architecture development team in FLAGSHIP 2020 project to develop Japanese flagship supercomputer “Fugaku” in RIKEN. He is a Professor（Cooperative　Graduate　School　Program）and Professor Emeritus of University of Tsukuba.

Calista Redmond RISC-V Foundation

Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Ravi Subramanian Mentor

Ravi Subramanian, vice president and general manager of Mentor’s IC Verification Solutions Division, was formerly the general manager of the company’s Analog/Mixed-Signal Verification business unit. He joined the company in 2014 with Mentor’s acquisition of Berkeley Design Automation (BDA), where he was president and CEO.  Prior to BDA he was vice president and general manager of the 3G WCDMA business unit at Infineon Technologies. He joined Infineon through the acquisition of Morphics Technology, a fabless semiconductor company where he was founder and vice president of Engineering, and later CEO.  He began his career at AT&T Bell Labs, where he won the AT&T Leadership Award.  He received his Bachelor of Science in Electrical Engineering from the California Institute of Technology and a Ph.D in Electrical Engineering &Computer Science from the University of California at Berkeley, where he was a recipient of the UC Regent’s Fellowship. He is the lead author on 18 U.S. patents on digital, analog and RF signal processing techniques in wireless and wireline communications. He is a charter member of TiE, a not-for-profit organization focused on fostering entrepreneurship across every generation all over the world. Every year since 2007, he has been selected to the Rutberg 200 Wireless Influencers List.

Zvonimir Z. Bandić Western Digital Corporation

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Zvonimir is Chairman of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.

Jerry Ardizzone Codasip

Over 35 years in the Semiconductor and Semiconductor IP Industry, having pent entire career in microprocessor and high performance semiconductor IP companies with 14 years at Motorola Semiconductor Director of Strategic Account Sales , 7 Years at ARM Inc, as President of ARM Inc and WW EVP of Sales, Tensilica / Cadence (SVP of Sales) and currently Vice President, WW Sales Codasip.

Philippe Notton EPI

Philippe Notton is a Senior Tech executive with strong technical and business background on Multimedia, Semiconductor and Security.

From Asian successful Startup to Large Industrial Groups with Entrepreneurial spirit, having worked in France, UK and USA with market leaders in their domain (Thomson, Canal+, LSI, MStar, ST), Philippe has a passion for High Technologies and fast paced environments.
Philippe Notton drove MStar Semiconductor SetTopBox Division from scratch to #3 worldwide creating from the ground the first Asian semiconductor player in the PayTV arena.
Before joining the European Processor Initiative, he was the head of the Consumer Division in ST Microelectronics (2400pers) designing SetTopBox chips and Consumer Asics.

Philippe Notton is GM of the European Processor Initiative but also CEO and Founder of SiPearl the company that gives life to the European Processor

 

Philippe Notton has an EE degree from SUPELEC , France (1993) and an Executive MBA from ESSEC , France and MANNHEIM, Germany (2008).

Jean-Marc Denis EPI

Since the beginning of 2018, Jean-Marc is the head of Strategy and Plan at Atos/Bull, in charge of the global cross-Business Unit Strategy and of the definition of the 3 years business plan. In addition, since the middle of 2018, Jean-Marc has been also elected as Chair of the Board of the European Processor Initiative (EPI).

Prior to that, Jean-Marc Denis took different positions in the HPC industry.

After five years of research in the development of new solvers for the for Maxwell equations at Matra Defense (France) as mathematician from 1990 to 1995, Jean-Marc Denis had several technical position in the HPC industry between 1995 to 2004 from  HPC pre-sales to Senior Solution Architect.

Since mid if 2004 Jean-Marc has worked at Bull SAS head Quarter (France) where he has started the HPC activity. In less than 10 years, the HPC revenue at Bull exploded from nothing in 2004 to 200M€ in 2015, making Bull the undisputed leader of the European HPC industry and the fourth in the world. From 2011 to the end of 2016, Jean-Marc has leaded the worldwide business activity with the goal to consolidate the ATOS/Bull position in Europe and to make ATOS/Bull a worldwide leader in Extreme Computing with footprint in Middle-East, Asia, Africa and South America.

In 2016 and 2017, Jean-Marc has been in charge of the definition of the strategy for the BigData Division at ATOS/Bull. In his position, his role is to define the global approach for the different BigData business lines covering HPC, Legacy (mainframe), Entreprise computing, DataScience consulting and Software.

In parallel to his activities at ATOS/Bull, since 2008, Jean-Marc Denis has taught “Supercomputer Architecture” concepts in Master 2 degree at the University of Reims Champagne Ardennes (URCA), France.

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Live News

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RT @HPC_Guru: .@EuProcessor readies prototype https://t.co/DxwuRnEg9C #HPC #AI #ARM #RISCV #FPGA @EuroHpc @TheNextPlatform https://t.co/…
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This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 826647

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