EPI Forum


EPI team has postponed EPI Forum due to the COVID-19 (Coronavirus).

As a European project, EPI follows and complies with the directives of the medical and health guidance of the relevant bodies: the World Health Organization (WHO), as well as of the national/local health authorities. We take health/welfare decisions (travel, working conditions, meetings) based on these guidelines.

New date of the EPI Forum will be announced at a later date.

EPI Forum Speakers

Thomas Skordas European Commission, DG CONNECT

Thomas Skordas received his diploma in Electrical Engineering in 1984 and a PhD in Computer Science in 1988. From 1988 to 1995, he worked in France as a Research Fellow and project leader in EU-funded R&D projects in the areas of Information Technology and Robotics.

In 1995, Thomas joined the European Commission as a Research Programme Officer in the Directorate General Information Society & Media (DG INFSO).  Ever since, Thomas worked in various units of DG INFSO (which, in 2012 became DG CONNECT) dealing with ICT research in the context of EU’s Research and Innovation Framework Programmes. From 2006 to 2009, he was Deputy Head of Unit in ICT Security and Trust. In 2009, he was appointed Head of the Photonics Unit and in 2014, Head of the Flagships Unit.

Since March 2017, Thomas is the Director of DG Connect’s “Digital Excellence and Science Infrastructure Directorate”.

Brent Gorda Arm, Inc.

Brent Gorda is the Senior HPC Executive for Arm, Inc. His responsibilities cover the world-wide business opportunities and evangelism in support of the Arm ecosystem. Brent has a history of disruptive change in High Performance Computing. Originally from Canada, Brent started as a compiler writer for parallel computing in the late 1980s. Much of his career has been with the US Department of Energy National Labs at Livermore and Berkeley. He was deeply involved in the transition from large vector systems to the parallel computing paradigm we have today, as well as the BlueGene architecture. An entrepreneur at heart, Brent co-founded Software Carpentry, (http://softwarecarpentry.org), originated the Student Cluster Competition (https://www.studentclustercompetition.us/) and was founder & CEO of Whamcloud, the company that kept Lustre in play for HPC (www.Whamcloud.com). After selling Whamcloud to Intel, Brent ran the High-Performance Data Division for several years.  Now at Arm, Brent is excited to help usher in the next generation of architectural choice for HPC, Cloud & Server computing.

Steve Scott Hewlett Packard Enterprise

Steve Scott is Senior Vice President, Senior Fellow, and Chief Technology Officer of HPC and AI at Hewlett Packard Enterprise, where he is responsible for guiding the long-term technical direction of computing, storage and analytics/AI products within the HPC & AI Business Unit.  Steve holds 42 US patents, and was the chief architect of several supercomputers and interconnects at Cray, which was acquired by HPE in 2019. He received the 2005 ACM Maurice Wilkes Award and the 2005 IEEE Seymour Cray Computer Engineering Award, and is a Fellow of the ACM and the IEEE.  Steve earned a BS in electrical and computer engineering, and a Masters and PhD in computer architecture, all from the University of Wisconsin Madison.

Paul de Bot TSMC Europe BV

Paul de Bot is Senior Director Emerging Business of TSMC Europe BV.

Starting his career in the area of video technology, Paul reached the position of Chief Strategy Officer of Philips Digital Networks.

In 2003 he joined Philips Semiconductors (later NXP Semiconductors) as Vice President Strategy & Business Development for their consumer, automotive and identification businesses, respectively.

Before joining TSMC, Paul had executive roles in the software industry and in corporate finance.

Paul holds MSc degrees in Electrical Engineering and Corporate Finance and a Professional Doctorate in Engineering.

Mitsuhisa Sato RIKEN Center for Computational Science

Mitsuhisa Sato is a deputy Director of RIKEN Center for Computational Science since 2018. He received the M.S. degree and the Ph.D. degree in information science from the University of Tokyo in 1984 and 1990.

From 2001, he was a professor of Graduate School of Systems and Information Engineering, University of Tsukuba. He has been working as a director of Center for computational sciences, University of Tsukuba from 2007 to 2013. Since October 2010, he is appointed to the research team leader of programming environment research team in Advanced Institute of Computational Science (AICS), renamed to R-CCS, RIKEN.

Since 2014, he is working as a team leader of architecture development team in FLAGSHIP 2020 project to develop Japanese flagship supercomputer “Fugaku” in RIKEN. He is a Professor(Cooperative Graduate School Program)and Professor Emeritus of University of Tsukuba.

Calista Redmond RISC-V Foundation

Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

Adrian Buckley Mentor, a Siemens Business

Adrian Buckley has held numerous roles during his 32-year tenure at Mentor ranging from technical support, presales applications through to sales management. Prior to his current position as VP Europe, Adrian was Director of Strategic Accounts. His Electronic Design Automation experience began at Tektronix where he was a key member of the newly formed Design Automation Division. After graduating from Newcastle University with an honors degree in physics and electronics, Adrian worked at the British Gas research laboratories before moving to BAE Dynamics. Here he gained experience on the suitability of micro-processors architectures for various military applications.

Zvonimir Z. Bandić Western Digital Corporation

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Zvonimir is Chairman of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.

Jerry Ardizzone Codasip

Over 35 years in the Semiconductor and Semiconductor IP Industry, having pent entire career in microprocessor and high performance semiconductor IP companies with 14 years at Motorola Semiconductor Director of Strategic Account Sales , 7 Years at ARM Inc, as President of ARM Inc and WW EVP of Sales, Tensilica / Cadence (SVP of Sales) and currently Vice President, WW Sales Codasip.

Philippe Notton EPI

Philippe Notton is a Senior Tech executive with strong technical and business background on Multimedia, Semiconductor and Security.

From Asian successful Startup to Large Industrial Groups with Entrepreneurial spirit, having worked in France, UK and USA with market leaders in their domain (Thomson, Canal+, LSI, MStar, ST), Philippe has a passion for High Technologies and fast paced environments.
Philippe Notton drove MStar Semiconductor SetTopBox Division from scratch to #3 worldwide creating from the ground the first Asian semiconductor player in the PayTV arena.
Before joining the European Processor Initiative, he was the head of the Consumer Division in ST Microelectronics (2400pers) designing SetTopBox chips and Consumer Asics.

Philippe Notton is GM of the European Processor Initiative but also CEO and Founder of SiPearl the company that gives life to the European Processor


Philippe Notton has an EE degree from SUPELEC , France (1993) and an Executive MBA from ESSEC , France and MANNHEIM, Germany (2008).

Jean-Marc Denis EPI

Since the beginning of 2018, Jean-Marc is the head of Strategy and Plan at Atos/Bull, in charge of the global cross-Business Unit Strategy and of the definition of the 3 years business plan. In addition, since the middle of 2018, Jean-Marc has been also elected as Chair of the Board of the European Processor Initiative (EPI).

Prior to that, Jean-Marc Denis took different positions in the HPC industry.

After five years of research in the development of new solvers for the for Maxwell equations at Matra Defense (France) as mathematician from 1990 to 1995, Jean-Marc Denis had several technical position in the HPC industry between 1995 to 2004 from  HPC pre-sales to Senior Solution Architect.

Since mid if 2004 Jean-Marc has worked at Bull SAS head Quarter (France) where he has started the HPC activity. In less than 10 years, the HPC revenue at Bull exploded from nothing in 2004 to 200M€ in 2015, making Bull the undisputed leader of the European HPC industry and the fourth in the world. From 2011 to the end of 2016, Jean-Marc has leaded the worldwide business activity with the goal to consolidate the ATOS/Bull position in Europe and to make ATOS/Bull a worldwide leader in Extreme Computing with footprint in Middle-East, Asia, Africa and South America.

In 2016 and 2017, Jean-Marc has been in charge of the definition of the strategy for the BigData Division at ATOS/Bull. In his position, his role is to define the global approach for the different BigData business lines covering HPC, Legacy (mainframe), Entreprise computing, DataScience consulting and Software.

In parallel to his activities at ATOS/Bull, since 2008, Jean-Marc Denis has taught “Supercomputer Architecture” concepts in Master 2 degree at the University of Reims Champagne Ardennes (URCA), France.

Luc Elman Synopsys

Luc Elman is Vice President Customer Excellence for the Design Group at Synopsys. He is responsible for customer enablement and support for Synopsys digital and analog design solutions in EMEA. Prior to that role, he served in various technical and management functions at Synopsys covering design implementation and verification.

He began his career as a design engineer and has held various technical and managing positions in EDA companies launching new innovative tools prior to joining Synopsys.

Luc Elman graduated from ESIEE, Paris and hold an MSc in electrical engineering from the California Institute of Technology, USA.

Sacha Vrazic Rimac Automobili

Sacha Vrazic is the Director of Autonomous Driving R&D at Rimac Automobili, where he works on redefining and solving issues for self-driving at extremely high speed. Previously, he was the Head of a Research Lab belonging in the Toyota Group companies, where he contributed to the Research of cutting-edge ADAS and fundamental research on future technologies. He was also for 7 years lecturer in an engineering school at Nice University, France.

Vrazic was always interested in creating disruptive technologies that will benefit the society, as writing a part of the history of the mobility is a fantastic opportunity, mixing science and philosophy. He is the author of numerous publications and patents and driven by the will to change the world. For him, it’s all about spatial mobility.

Romain Dolbeau EPI

Romain Dolbeau is a Distinguished Expert at Atos-Bull. After studying computer architecture at Université Paris XI, Université Rennes 1 and ENS Cachan, Romain co-founded and joined CAPS entreprise, a pioneer company in compilation that introduced directive-based programming for heterogeneous computing with the HMPP technology. Romain joined Bull in 2014 as an HPC expert, helping customers leverage both CPU and accelerators to get the best performance out of their supercomputers. Since late 2018, Romain is working as the lead software architect for the EPI project.

Yingchih Yang EPI

Lead Architect for the EPI project. Yingchih YANG is the CTO of the newly formed SiPearl startup, and he has been leading the GPP chip designing activities.  He worked from Atos-Bull for the EPI project, after his position as the adv. technology officer in the consumer digital division of STMicroelectronics France during 2015-2018.  Before that he was the head of engineering teams for settopbox chip product line in MediaTek-MStar, and CTO of Sunplus Technology in Taiwan.

Jesús Labarta EPI

Professor Jesús Labarta has been full professor of Computer Architecture at UPC since 1990 and was Director of CEPBA-European Center of Parallelism at Barcelona from 1996 to 2005. Since its creation in 2005, he has been the Director of the Computer Sciences Research Department within the Barcelona Supercomputing Center (BSC).

During his 35-year academic career, Prof. Labarta has made significant contributions in programming models and performance analysis tools for parallel, multicore and accelerated systems, with the sole objective of helping application programmers to improve their understanding of their application’s performance and to improve programming productivity in the transition towards very large-scale systems. His research team has been developing performance analysis and prediction tools (Paraver and Dimemas) and pioneering research on how to increase the intelligence embedded in these performance tools.

He has also been a driving force behind the task-based StarSs programming model, which gives runtime systems the required intelligence to dynamically exploit the potential parallelism and resources available. His team has influenced the evolution of the OpenMP standard with the OmpSs instantiation of StarSs, and, in particular, its tasking model.

He has constantly tried to incorporate his vision and ideas into industrial collaborations. Currently Prof. Labarta is the leader of the Performance Optimization and Productivity (POP) EU Center of Excellence where users (both academic and SMEs) from a very wide range of application sectors receive performance assessments and suggestions for code refactoring efforts. He also leads within the EPI project the activities (hardware and software) on the RISC-V vector accelerator

In Nov 2018, he was awarded by The Association for Computing Machinery (ACM) and IEEE Computer Society (IEEE CS) with the ACM-IEEE CS Ken Kennedy Award for his seminal contributions to programming models and performance analysis tools for high performance computing. He’s the only non US Researcher receiving this award.

Pierre Chehwan NAVYA Group

Pierre Chehwan is Director of Strategic-Alliance and Institutional Relationship at NAVYA Group. His mission is to support institutions and governments regarding Autonomous Vehicles, legal framework, and related funded projects from European Union or governmental as well as building strategic alliances. With 27 years of experience in fast paced technologies within market game changer companies, he worked in entrepreneurial pioneer startups, as well as international organisation challengers.  Pierre contributed to 2 major disruptive technologies that changed our daily lives: the birth of Internet and the rise of the mobile phone. Today he is contributing to the 3rd one : Autonomous Vehicles.

Before joining NAVYA, he worked 7 years for one of the first internet providers in Europe. Then he moved for more than 10 years in the mobile industry as head of product strategy for Tier 1 operators at Alcatel Mobile Phones and Sales Director at Huawei. He developed later the B2B Mobile business of Ingram Micro. Today, Pierre is handling Strategic Alliance as well as EU & Public affairs within NAVYA to make our cities greener with Autonomous Vehicles.

Stéphane Requena GENCI

Stéphane Requena is CTO of GENCI (Grand Equipement National de Calcul). At the end of his studies in distributed and parallel computing, he first joined CISI as an HPC engineer in the energy sector (EDF, CEA) and then IFPEN to initially optimize and parallelize applications in the field of oil exploration and then set up within the IT department the migration from Unix to Linux (workstations, computing cluster). He then joined GENCI in 2007 just after its creation and follows in particular GENCI’s technology watch activity, the technical management of calls for tenders to regularly upgrade the HPC/storage resources within the 3 national centres (CINES, IDRIS, TGCC) and the development of new services.

It has also been involved since its creation in 2010 in the European computing infrastructure PRACE and in European initiatives/projects such as EuroHPC, PRACE-IP, EESI, EXDCI, Mont-Blanc, PPI4HPC or recently EPI.

With more than 20 years of expertise in HPC, HPC, AI, computing architectures, oil simulation and fluid mechanics, Stéphane is passionate about technology and science. He observes the convergence between HPC, HPDA and AI which are for Stéphane an accelerator of scientific discoveries!

Robert J. Hoekstra Sandia National Laboratories

Dr. Robert J. Hoekstra leads the scalable architectures research department in Sandia National Laboratories Center for Computing Research(CCR). Robert received his doctorate in electrical and computer engineering from the University of Illinois Urbana-Champaign(UIUC) in 1998. His early research focused on high fidelity modeling of design and manufacturing for semiconductors. Over the last decade, he has led a broad range of HPC R&D including electrical systems modeling, applied mathematics, scalable algorithms and scalable architectures. Robert currently leads the Sandia’s efforts to explore innovative HPC architectures for the US DOE/NNSA Advanced Simulation and Computing program in support of the US Exascale Computing Project and the National Strategic Computing Initiative. This is highlighted by the recent deployment of the first Arm-based petascale supercomputer, Vanguard/Astra.

Mario Kovač EPI

Prof. Mario Kovac is full professor at the Faculty of Electrical Engineering and Computing (FER), University of Zagreb, Croatia. In 1990 and 1991 he received a VLSI and Computer Architecture Scholarship at the University of South Florida, and he subsequently received the Fulbright Award in 1993.

He holds several patents including US patents in multimedia systems and architecture domains.

In 2008, Croatian President awarded him with the the Medal of Honor “Order of Danica Hrvatska with the image of Ruđer Bošković” for special merit in science. He currently holds several positions: Chief Communications Officer (CCO) at European Processor Initiative; Expert member of Governing Board as well as Research and Innovation Advisory Group Observer Member at EuroHPC Joint Undertaking; Director HPC Architectures and Applications Research Center at FER. He is senior member of the IEEE Computer Society.

Contacts: mario.kovac@fer.hr      http://www.linkedin.com/in/mariokovac

Steve Langridge HiSilicon Technologies Co., Ltd.

Steve excelled in technical leadership positions at IBM Canada for over 20 years before joining Huawei in 2013 where he founded the Toronto Research Center.  As Director, Hardware Acceleration Dept, Steve created and led a global team of Hardware Acceleration experts in HW/SW Co-Design. Now, Steve is helping to develop HiSilicon’s business in North America and Europe for strategic ICT markets.  Steve continues to work closely with Semiconductor Research, microprocessor, accelerator and software ecosystem partners in pursuit of highly efficient and extreme value processing for clients.

Dominik Reinhardt EPI

Dr.-Ing. Dominik Reinhardt has more than 10 years working experience with BMW AG in Munich, 6 years as a software engineer for system functionality (BMW AUTOSAR Core Team) and 2 years responsible for 32bit microcontrollers at BMW within team of semiconductor standards. He also represented BMW AG within the ARAMiS research project for embedded multicore technology (German BMBF funded).

Currently, in the last two years, he has been working as a research engineer at BMW’s central research division in Garching. He is the project lead for Computing Platforms (modular integration platforms) and represents BMW AG within the European Processor Initiative research project (EU-funded).




Live News

.@ZonaCesarini (@Cineca1969) and Franz Josef Pfreundt (@FraunhoferITWM) participated at a session titled “Can fast be green? Opportunities and challenges for Europe when making HPC sustainable” at @Supercomputing. Here you can read more👇 https://t.co/oq7W80sqYb
02/12/2021 8:36 am
29/11/2021 12:00 pm
Lilia Zaourar Koutchoukali from @CEA_Officiel is going to have a presentation today titled "Multilevel Simulation-Based Co-Design of Next Generation HPC Microprocessors" at #SC21. More information about the presentation here ⬇ https://t.co/14WZgSnqsw
15/11/2021 9:43 am
Benoît Dupont de Dinechin from @Kalrayinc had a keynote talk at #CSWAutumn21! @hipeac 📢 Attendees had an opportunity to hear more about EPI project and about the interesting work that we do. 💪 https://t.co/EOesLyTpcr
26/10/2021 8:30 am
@Evolve_H2020 has two interesting webinars in the upcoming weeks! 📢 ➡️Consolidating Storage Technologies in an HPC-Enhanced Kubernetes Platform and ➡️Automotive Data Analytics with EVOLVE (2). More information about the webinars and registration here: https://t.co/y2kXiUjfDa
18/10/2021 9:30 am
@technomorous No problem🙃
14/10/2021 7:05 am
@technomorous Hello and sorry for the wait! 🙃 Our RSS feed is here: https://t.co/cE6iHtagPH.
13/10/2021 11:38 am
Great talk from @Calista_Redmond (@risc_v) with The New Stack during the Open Summit 2021 event! 💪 EPI project and the work that we have been doing were also mentioned in the presentation. 📢 Full presentation is here ➡️ https://t.co/6qRbDma5sT https://t.co/R5JocP2CyC
08/10/2021 8:43 am
@technomorous Hello, we are working on it! 🙃 We expect it to soon be up and running. Also, we'll let you know here when it is done!
05/10/2021 11:10 am
.@SIPEARL_SAS opens design center in Grenoble ⬇ https://t.co/Snx2lrqkS0
29/09/2021 12:35 pm

EPI EPAC1.0 RISC-V Test Chip Samples Delivered

Another step closer to demonstrate the capabilities of a RISC-V based European microprocessor The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC1.0 RISC-V Test Chip samples were delivered […]

Eric Monchalin is the new Chairman of the EPI Board

General Assembly of European Processor Initiative has selected a new Chairman of the Board in July. Eric Monchalin from Atos, the company that coordinates the EPI project, is going to lead 28 partners from 10 countries in their efforts to design and implement a roadmap for a new family of low-power European processors. Eric is […]

EuroHPC JU regulation published in the Official Journal of the European Union

Regulation on EuroHPC JU establishment adopted

EPI to take centre stage at the ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications

Taking place on 30 August – 3 September 2021, the second ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications will be co-hosted by Barcelona Supercomputing Center (BSC), in conjunction with the Universitat Politècnica de Catalunya – Barcelona Tech (UPC). The programme of this year’s summer school, which will be fully […]

EPI EPAC1.0 RISC-V Test Chip Taped-out

European Processor Initiative has successfully released EPAC1.0 Test Chip for fabrication

Infineon’s Knut Hufeld Discusses Automotive Developments in EPI

Knut Hufeld, Senior Director R&D with Infineon and an Automotive Stream representative in EPI, talked about the developments in the stream with Ralf Hartmann. 

EPI EPAC1.0 RISC-V core boots Linux on FPGA

EPI team successfully boots Linux on our EPAC 1.0 core subset implemented on FPGA.

EPI team at HiPEAC 2021

EPI team participated in several activities at HIPEAC2021.

EPI and European Exascale Projects at Supercomputing

European Processor Initiative and EU exascale projects will share a virtual booth at Supercomputing2020.

European Processor Initiative: Second year of activities

The European Processor Initiative https://www.european-processor-initiative.eu/, a project with 27 partners from 10 European countries, with the goal of helping the EU achieve independence in HPC technologies, is finishing its second year of activities. The project is unveiling an updated roadmap and announcing a virtual booth at Supercomputing.
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