EPI Forum 2025 - European Processor Initiative

EPI FORUM IN PARIS REGISTER NOW FOR EVENT ON 6-7 OCT, 2025 - EARLY BIRD UNTIL SEP 7

The European Processor Initiative is announcing its annual EPI Forum. It is to be held 6-7 October, 2025 in Paris, France.

It will be held at the magnificent Hotel Arts et Métiers, 9bis Avenue d’Iéna, 75016 Paris, France.

EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative.

Early bird registration ends on September 7th, find details below and catch the better price now!

More organizational details to follow, including announcements of keynotes and agenda – stay tuned!

REGISTRATION – EARLY BIRD UNTIL SEP 7!

Early bird registration is now open, and the early bird fee is active until September 7th. The early bird fee is 80 EUR, VAT included, and REGISTRATION is done via the following link:

CLICK HERE TO REGISTER!

Registration is done based on first come, first served basis, until venue capacity is filled, so we recommend early registration. Full price in September will be upped to 160 EUR, VAT included.

CANCELLATION AND DATA PRIVACY POLICY

If you are unable to attend, please have a look at our cancellation policy:

EPI FORUM REGISTRATION AND CANCELLATION POLICY 2025

PRESS

If you are a member of the press, please do not use this link to register. Instead, e-mail us at epi-forum [at] european-processor-initiative.eu.

VENUE

The venue of the event is L’Hôtel des Arts & Métiers, Paris.

AGENDA

The Forum starts on 6 October and finishes at October 7, 2025.

The main theme of discussion will be European technologies for true digital and AI freedom:

• Empowering European Digital and AI Sovereignty
• Breaking HPC silos
• Driving Sustainability in HPC, Edge Computing, and AI

The Organizing committee reserves the right to implement changes to the Agenda. Should you have any inquiries related to the EPI Forum, please contact us at
epi-forum [at] european-processor-initiative.eu.

Click on the image below to get a full-screen agenda draft!

EPI FORUM IS SPONSORED BY

EPI Forum speakers In alphabetical order

David Atienza EPFL

David Atienza is a professor of Electrical and Computer Engineering, Associate Vice President of multi-disciplinary research centers and technology platforms, and Head of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. Previously, he was the Scientific Director of the EcoCloud Sustainable Computing Center at EPFL. He received his M.Sc. and Ph.D. degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium).

His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) architectures and low-power edge AI systems, including architectures and thermal-aware designs for many-core servers and data centers. He is a co-author of more than 400 papers, two books, and has 14 licensed patents in these topics.

He served as DATE General Chair and Program Chair, and is currently Editor-in-Chief of IEEE TCAD and ACM CSUR. Among others, Dr. Atienza has received the CODES+ISSS 2024 Test-of-Time Best Paper Award, the ICCAD 2020 10-Year Retrospective Most Influential Paper Award, the 2018 DAC Under-40 Innovators Award, and an ERC Consolidator Grant. He is a Fellow of IEEE, a Fellow of ACM, served as IEEE CEDA President (period 2018-2019), and was the Chair of the European Design Automation Association (EDAA) between 2022 and 2024.

Elisabetta Boella E4

Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 and her Ph.D. in Computational Plasma Physics in 2014, both from Politecnico di Torino (Turin, Italy). She is currently an HPC Product Specialist at E4 Computer Engineering (Scandiano, Italy), where she coordinates and leads the company contributions to several European research projects, including MaX, SPACE, and EoCoE. Her professional expertise lies at the intersection of high-performance computing and scientific applications, with research interests that include numerical modelling, parallel programming, and hardware–software co-design practices for emerging architectures.

She has extensive experience in the development and optimisation of large-scale parallel applications using the Message Passing Interface (MPI), and is one of the main developers of ECsim, a massively parallel plasma simulation code. In addition, she has significant expertise in Grpahical Processing Unit (GPU) programming and in porting legacy applications to heterogeneous architectures.

Carlo Cavazzoni Leonardo

Carlo is the Head of Leonardo Hypercomputing Continuum @ Leonardo.com. Before joining Leonardo in May 2020, he spent more than 20 years in Cineca (Italian supercomputing centre) dealing mainly with support of user communities and EU initiatives. From an education stand point, he holds a PhD in physics from SISSA/ISAS international schools. He is presently a member of the ETP4HPC steering board, and Leonardo representative in the European Alliance for Industrial Data, Edge and Cloud. He has collaborated with different user communities to enable applications on massively parallel HPC systems and innovative architecture solutions. He is author and co-author of more than 100 peer review articles, including Science, Physical Review Letters, Nature Materials, and many others.

Marc Duranton CEA

Dr. Marc Duranton is Senior Fellow of CEA and member of the Digital Systems and Integrated Circuits Division of CEA, where he is involved in realizations (hardware accelerators and software tools) for Artificial Intelligence and for distributed systems from IoT to HPC.

He previously worked in Philips and NXP where he led the development of the family of L-Neuro chips, digital processors using artificial neural networks and on several video coprocessors for the VLIW processor TriMedia.

His interests include High Performance Computing, Deep Learning, distributed and embedded Artificial Intelligence systems, emerging paradigms for computing systems, distributed and federated computing, models of computation and communication with time guaranties. He is in charge of the roadmap activities of the HiPEAC community ( https://www.hipeac.net/vision/ ) and is involved in the SRA of the European Technology Platform for High Performance Computing (ETP4HPC SRA) and in the Strategic Research and Innovation Agenda of the Electronics Components and Systems (ECS SRIA).

Filippo Mantovani BSC

Filippo Mantovani is an established researcher leading the Mobile and Embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He holds a Ph.D. in Computer Science from the University of Ferrara, Italy, and has worked as a scientific associate at DESY in Zeuthen, Germany, and the University of Regensburg, Germany. His career has focused on computational physics and high-performance computing, contributing to projects like Janus, QPACE, and Mont-Blanc. Currently, he is involved in the FPGA prototyping tasks of RISC-V-based accelerators within the European Processor Initiative (EPI) and leads the collaboration between BSC and Etxe-tar to optimize high-throughput manufacturing systems.

Jean-Philippe Nominé CEA

Dr. Jean-Philippe Nominé – CEA Fellow, HPC Strategic Collaborations Manager – Computing Centres, Sofware and Codes Division, CEA/DIF Bruyères-le-Châtel.

Since more than 15 years, after different technical and managing positions in CEA HPC division, in particular in software development and engineering and high performance visualization, Dr. Nominé has mostly focused on the development of European HPC activities. He contributed in particular to the early development and operations of PRACE aisbl, of ETP4HPC Association, of Horizon 2020 HPC Public Private Partnership, and to various technical or ecosystem development European HPC projects.

Dr. Nominé is a member of ETP4HPC Association Steering Board, and was Chair of EuroHPC Research and Innovation Advisory Group (RIAG) in 2022-2023, on behalf of ETP4HPC.

Philippe Notton SiPearl

Passionate about high technology and fast-moving environments, Philippe Notton has worked in France, the UK and the US for market-leading groups (Thomson, Canal+, LSI Logic, STMicroelectronics, Atos), as well as a successful startup, MStar Semiconductor.

His original vision of SiPearl came in 2015 while he was leading a division of 2,400 engineers at STMicroelectronics. In 2017, Philippe joined Atos to help set up the EPI consortium. In June 2019, he launched SiPearl as a spin-off of the EPI with the support of the European Union.

Philippe holds an engineering degree from Supélec and an Executive MBA from Essec and Manheim.

Craig Prunty SiPearl

A product marketing expert in the global high-performance computing (HPC) market, Craig Prunty has spent most of his career with global semiconductor companies (Marvell Semiconductor, Cavium, AppliedMicro), contributing to the commercial success of several product lines. In his various positions, he has been engaged in industry consortiums and has built up a robust global network of partners

Prior to moving to SiPearl, Craig was Marketing Director for Marvell Semiconductor’s server processors division. He has successfully developed new markets including high-performance computing harnessing Arm technology.

A dual French and American national, Craig has a Master in Electrical Engineering from San Diego State University.

Lilia Zaourar CEA

Dr. Lilia Zaourar is a CEA expert in co-design techniques for Computing Architectures at CEA LIST. She received an MS and PhD in Operational Research and Computer Science from the University Joseph Fourier, Grenoble, in 2007 and 2010, respectively. She developed various optimization algorithms for the design and test of integrated circuits. Then, she was a temporary teaching and research assistant at the SoC department in Computer Science PARIS 6 Laboratory, Sorbonne University, from 2010 to 2012. She was involved in developing optimization strategies for the resource-sharing problem to test embedded memories. She joined the CEA LIST in 2012 and has participated in various national, European, and industrial research projects on real-time mixed-criticality systems, optimization strategies of runtime software for heterogeneous HPC and microservers, and FPGA emulation.

She led Modelling and Simulation activities within the first phase of the European Processor Initiative (EPI) project. She is currently involved in the second phase of EPI on co-design and exploration. Her research interests cover combinatorial optimization and operational research techniques with a special focus on optimization problems for electronic design automation and high-performance embedded systems, as well as testing and security. She is the leader of the working group ” Optimized Integreted Circuit ” funded by the French institution CNRS. She has been a SAMOS, SC, PMBS, and CoDit technical programs member. She has served as General Chair for Hipeac/Rapido 2023, 2024, and General Chair of the 50th Euromicro DSD/SEAA 2024 conference. Since 2025, she is vice chair of the French chapter IEEE CEDA.

Materials from 2024 Barcelona forum edition

The European Processor Initiative held its first Forum on 9 and 10 October, 2024, in Barcelona, Spain.

EPI Forum gathered experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers who discussed and presented EPI’s achievements so far and future developments in the Initiative.

Agenda of the event that was held can be found here: EPI FORUM AGENDA,

while the presentations and materials are available in our repository here:

https://www.european-processor-initiative.eu/dissemination-material/epi-forum-in-barcelona/

EPI Forum organizing committee wishes to thank the sponsors, speakers and panelists listed below for participating and making it a successful event. Stay tuned for announcements of the second EPI Forum next year!

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