The European Processor Initiative is announcing its annual EPI Forum. It is to be held 6-7 October, 2025 in Paris, France.
It will be held at the magnificent Les salons de l’Hôtel des Arts & Métiers, 9bis Avenue d’Iéna, 75016 Paris, France.
EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative.
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CANCELLATION AND DATA PRIVACY POLICY
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EPI FORUM REGISTRATION AND CANCELLATION POLICY 2025
PRESS
If you are a member of the press, please do not use this link to register. Instead, e-mail us at epi-forum [at] european-processor-initiative.eu.
VENUE
The venue of the event is Les salons de l’Hôtel des Arts & Métiers, Paris.
AGENDA
The Forum starts on 6 October and finishes at October 7, 2025.
The main theme of discussion will be European technologies for true digital and AI freedom:
• Empowering European Digital and AI Sovereignty
• Breaking HPC silos
• Driving Sustainability in HPC, Edge Computing, and AI
The Organizing committee reserves the right to implement changes to the Agenda. Should you have any inquiries related to the EPI Forum, please contact us at
epi-forum [at] european-processor-initiative.eu.
Click on the image below to get a full-screen agenda draft!
Jean-Thomas successively worked for Intel, the University of Versailles, and the French Atomic Commission (CEA). He participated to the creation of their joint laboratory on Exascale Research. At DDN, Jean-Thomas’ role includes overseeing research collaborations in Europe as well as product management for some advanced DDN’s solutions.
David Atienza is a professor of Electrical and Computer Engineering, Associate Vice President of multi-disciplinary research centers and technology platforms, and Head of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. Previously, he was the Scientific Director of the EcoCloud Sustainable Computing Center at EPFL. He received his M.Sc. and Ph.D. degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium).
His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) architectures and low-power edge AI systems, including architectures and thermal-aware designs for many-core servers and data centers. He is a co-author of more than 400 papers, two books, and has 14 licensed patents in these topics.
He served as DATE General Chair and Program Chair, and is currently Editor-in-Chief of IEEE TCAD and ACM CSUR. Among others, Dr. Atienza has received the CODES+ISSS 2024 Test-of-Time Best Paper Award, the ICCAD 2020 10-Year Retrospective Most Influential Paper Award, the 2018 DAC Under-40 Innovators Award, and an ERC Consolidator Grant. He is a Fellow of IEEE, a Fellow of ACM, served as IEEE CEDA President (period 2018-2019), and was the Chair of the European Design Automation Association (EDAA) between 2022 and 2024.
Dr. Karim Azoum has a PhD in Science with deep expertise in emerging technologies such as Quantum Computing, High-Performance Computing (HPC), Artificial Intelligence, IoT, Big Data, Simulation, and Blockchain. I work at the intersection of technology and innovation, supporting the development of dynamic ecosystems involving large corporations, SMEs, startups, and research institutions.
He is the Program Director at Teratec, a leading association dedicated to high-performance simulation. He leads the EuroCC project especially the French national Center CC-FR.
Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 and her Ph.D. in Computational Plasma Physics in 2014, both from Politecnico di Torino (Turin, Italy). She is currently an HPC Product Specialist at E4 Computer Engineering (Scandiano, Italy), where she coordinates and leads the company contributions to several European research projects, including MaX, SPACE, and EoCoE. Her professional expertise lies at the intersection of high-performance computing and scientific applications, with research interests that include numerical modelling, parallel programming, and hardware–software co-design practices for emerging architectures.
She has extensive experience in the development and optimisation of large-scale parallel applications using the Message Passing Interface (MPI), and is one of the main developers of ECsim, a massively parallel plasma simulation code. In addition, she has significant expertise in Grpahical Processing Unit (GPU) programming and in porting legacy applications to heterogeneous architectures.
Raphaël Brochard is an entrepreneur driven by innovation and sustainability. Raised in Paris, he moved to the U.S. at 18, earning a Bachelor of Science from Texas State University before starting his career in tech at Apple and Indeed. After a decade abroad, he returned to France to launch his first company.
Raphaël’s curiosity led him to start a new entrepreneurship adventure… He joined forces with his father, Luigi Brochard, and partner Julita Corbalan, to develop EAR: Energy Aware Runtime.
Carlo is the Head of Leonardo Hypercomputing Continuum @ Leonardo.com. Before joining Leonardo in May 2020, he spent more than 20 years in Cineca (Italian supercomputing centre) dealing mainly with support of user communities and EU initiatives. From an education stand point, he holds a PhD in physics from SISSA/ISAS international schools. He is presently a member of the ETP4HPC steering board, and Leonardo representative in the European Alliance for Industrial Data, Edge and Cloud. He has collaborated with different user communities to enable applications on massively parallel HPC systems and innovative architecture solutions. He is author and co-author of more than 100 peer review articles, including Science, Physical Review Letters, Nature Materials, and many others.
Mr. Nikolaos Dimou (male) is a Senior Research Engineer at the Computer Architecture and VLSI Systems (CARV) Laboratory of the Institute of Computer Science (ICS) at FORTH. He holds a BSc in Physics (NKUA, 2013) with a specialization in Electronics, Computers, Telecommunications and Control and an MSc in Control and Computing (NKUA, 2016). His interests focus on the architecture and design of multicore systems, reconfigurable computing, interconnection networks and memory hierarchy, particularly in the context of High-Performance Computing (HPC). His work often intersects with advanced semiconductor technologies, contributing to projects that involve the development of hardware architectures crucial for optimizing computational performance in real systems. He has contributed to the IC design and verification of the EU-funded EPI, EUPILOT and eProcessor projects. Additionally, he is deeply involved in the development of several FPGA-based hardware prototypes for EU-funded projects, including EPI, EUPILOT, eProcessor, EuroExa, ExaNeSt, ExaNoDe, and ECOSCALE.
Dr. Marc Duranton is Senior Fellow of CEA and member of the Digital Systems and Integrated Circuits Division of CEA, where he is involved in realizations (hardware accelerators and software tools) for Artificial Intelligence and for distributed systems from IoT to HPC.
He previously worked in Philips and NXP where he led the development of the family of L-Neuro chips, digital processors using artificial neural networks and on several video coprocessors for the VLIW processor TriMedia.
His interests include High Performance Computing, Deep Learning, distributed and embedded Artificial Intelligence systems, emerging paradigms for computing systems, distributed and federated computing, models of computation and communication with time guaranties. He is in charge of the roadmap activities of the HiPEAC community ( https://www.hipeac.net/vision/ ) and is involved in the SRA of the European Technology Platform for High Performance Computing (ETP4HPC SRA) and in the Strategic Research and Innovation Agenda of the Electronics Components and Systems (ECS SRIA).
Alexandra Kourfali is a Programme Manager of Research and Innovation at the EuroHPC Joint Undertaking, focused on the Technology pilar and managing the chips projects. She received her MSc degree in Computer Engineering from the University of Thessaly, Greece, and her Ph.D. in Computer Engineering from Ghent University, Belgium, in 2019. Previously she held academic appointments at Ghent University, Stuttgart University, the Barcelona Supercomputing Center, and the European Space Agency, and non-academic appointments at Thales, Belgium. Her interests include High-Performance Computing, reconfigurable computing, hardware reliability, and computer architectures with an emphasis on RISC-V.
Mario Kovač is full professor at the Faculty of Electrical Engineering and Computing (FER), University of Zagreb, Croatia and Director of HPC Architectures and Applications Research Center at FER. He received his PhD in computer science and engineering from the same university in 1995. He was awarded Fulbright scholar award for Computer Science and Engineering Research that he spent at the University of South Florida, Tampa, USA between 1990 and 1994. His special focus was on efficient chip implementation of architectures for image, video and math computation processing that led to several chips including Jaguar chip. He holds several US and international patents in multimedia and architecture domains. His work on architectures and efficient execution was focused over time in several industry domains: multimedia systems, large national/cross-national health-care systems, electric cars and other. In 2008, Croatian President awarded him with the Medal of Honor “Order of Danica Hrvatska with the image of Ruđer Bošković” for special merit in science. His professional activities throughout years were always intertwined combination of science and industry activities. He was President/Vice-president of the Board and CxO of several organisations and companies where he was primarily involved in strategic management and R&D.
A seasoned professional with over 30 years of experience in project management and developing relationships with major French accounts, I have dedicated most of my career to supporting the digital transformation of leading enterprises in France. My journey includes holding strategic roles such as 7 years at SUN Microsystems, where I led large-scale technology projects, followed by 11 years at Google Cloud France, where I was the founder and Country Manager. In that role, I had the honor of launching and structuring the French entity, establishing Google Cloud as a key player in cloud computing for major French enterprises.
Jean-Francois Lavignon is the president of TS-JFL.
His previous experience includes being Vice-Chairman of the ITEA4. He was also a Director at Bull for 18 years.
With over 30 years of experience driving growth and innovation in the global IT and telecom sectors, Emmanuel has held several positions from R&D, engineering and business functions to executive positions, becoming a key leader in the high-performance, computing and AI ecosystem.
A graduate from High Engineering school in Electronics and Computer Sciences in Rennes (France) and from the business school INSEAD, Emmanuel began his career in R&D and Engineering positions in Telecom Wireless division at Nortel in Paris as Software designer, R&D team management and architecture leader. He rapidly advanced from the R&D and Engineering community to senior leadership roles, overseeing global product management and strategic alliances.
When joining Bull in 2010, Emmanuel developed key strategic partnerships with industry leaders, resellers and OEMs ensuring strong and rapid business growth. After Bull’s acquisition by Atos in 2014 (later on hosted under the Eviden brand), Emmanuel led the Enterprises Servers business and then the Big Data Platforms activity, with the responsibility to redefine the business to increase revenue and profitability through global strategy, new go-to-market approach and strategic acquisitions,
Since 2022, as Group SVP of Advanced Computing at Eviden (Atos Group), he leads a billion-dollar P&L, championing Europe’s first Exascale machines and expanding cloud, HPC, and AI solutions and services. His leadership is pivotal in advancing European technological sovereignty while accelerating market success in APAC, Latin America and the US.
Committed to fostering innovation and technological advancement, Emmanuel also serves as a board member for SiPearl, DataSentics, and S+C, all prominent European startups developing sovereign AI solutions.
Emmanuel’s LinkedIn profile: https://www.linkedin.com/in/emmanuelleroux/
Dr. Manolis Marazakis (Ph.D. in Computer Science, University of Crete, 2000) is a Principal Staff Research Scientist at the Institute of Computer science, FORTH. His research interests are in architectures and efficient systems software, mainly resource management and storage I/O middleware, for high-performance servers in data center environments. He has contributed to the design, implementation and performance analysis of several system prototypes for HPC, data analytics,
multi-tenant workloads, and the convergence of HPC and Cloud infrastructures. Since 2018, he has been contributing to codesign activities within the European Processor Initiative. Since 2019, he has been a contributor to successive versions of the Strategic Research Agenda for HPC being developed by the ETP4HPC Association, mainly in the area of system software and management.
Currently, he is coordinating projects that aim to build data-center systems based on chips from ongoing European projects funded by the EuroHPC JU. He is a senior member of ACM and IEEE, and a member of the USENIX Technical Society.
[ more information: https://www.linkedin.com/in/mmarazakis ]
Filippo Mantovani is an established researcher leading the Mobile and Embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He holds a Ph.D. in Computer Science from the University of Ferrara, Italy, and has worked as a scientific associate at DESY in Zeuthen, Germany, and the University of Regensburg, Germany. His career has focused on computational physics and high-performance computing, contributing to projects like Janus, QPACE, and Mont-Blanc. Currently, he is involved in the FPGA prototyping tasks of RISC-V-based accelerators within the European Processor Initiative (EPI) and leads the collaboration between BSC and Etxe-tar to optimize high-throughput manufacturing systems.
Eric Monchalin is Vice-President, Head of Machine Intelligence at Eviden and Chair of the European Processor Initiative. At Eviden, he is responsible for creating and finalizing new technological and business initiatives for the Big Data and Security Global Business Line. His career has been built on numerous R&D positions in the areas of embedded systems, communication, storage, AI, edge and high-performance computing. He is a technology-minded person who has a wide range of skills and technological knowledge and is fully focused on turning customers’ wishes into reality.
Dr. Jean-Philippe Nominé – CEA Fellow, HPC Strategic Collaborations Manager – Computing Centres, Sofware and Codes Division, CEA/DIF Bruyères-le-Châtel.
Since more than 15 years, after different technical and managing positions in CEA HPC division, in particular in software development and engineering and high performance visualization, Dr. Nominé has mostly focused on the development of European HPC activities. He contributed in particular to the early development and operations of PRACE aisbl, of ETP4HPC Association, of Horizon 2020 HPC Public Private Partnership, and to various technical or ecosystem development European HPC projects.
Dr. Nominé is a member of ETP4HPC Association Steering Board, and was Chair of EuroHPC Research and Innovation Advisory Group (RIAG) in 2022-2023, on behalf of ETP4HPC.
Passionate about high technology and fast-moving environments, Philippe Notton has worked in France, the UK and the US for market-leading groups (Thomson, Canal+, LSI Logic, STMicroelectronics, Atos), as well as a successful startup, MStar Semiconductor.
His original vision of SiPearl came in 2015 while he was leading a division of 2,400 engineers at STMicroelectronics. In 2017, Philippe joined Atos to help set up the EPI consortium. In June 2019, he launched SiPearl as a spin-off of the EPI with the support of the European Union.
Philippe holds an engineering degree from Supélec and an Executive MBA from Essec and Manheim.
Jean-Pierre Panziera the Chief Technology Director for High Performance Computing at Eviden, an Atos business. He joined Bull, now part of Eviden, in 2009, and is responsible for future HPC hardware developments. He started his career at Elf-Aquitaine as a research developer for seismic processing. After joining a couple of startups in the Silicon Valley, he worked for 20 years at SGI where he held various position in the USA and in Europe, first as an HPC application specialist and later as a Chief Engineer.
He is also the Chairman of the ETP4HPC association which represents the HPC ecosystem in Europe and he is a member of EuroHPC Joint Undertaking Governing Board.
Jean-Pierre holds an engineer degree from Ecole Nationale Supérieure des Mines de Paris.
A product marketing expert in the global high-performance computing (HPC) market, Craig Prunty has spent most of his career with global semiconductor companies (Marvell Semiconductor, Cavium, AppliedMicro), contributing to the commercial success of several product lines. In his various positions, he has been engaged in industry consortiums and has built up a robust global network of partners
Prior to moving to SiPearl, Craig was Marketing Director for Marvell Semiconductor’s server processors division. He has successfully developed new markets including high-performance computing harnessing Arm technology.
A dual French and American national, Craig has a Master in Electrical Engineering from San Diego State University.
Stephen Robotham is a senior business development manager in AMD’s Datacenter Business Unit, with over 13 years of experience in HPC and AI. He leads strategic customer and partner engagements across EMEA, helping define and deliver GPU solutions for advanced computing. Stephen works closely with engineering and product teams to align regional customer needs with AMD’s technology roadmap, supporting deployments at some of the most advanced data centres in the region.
Estela Suarez is Joint Lead of the department Novel System Architecture Design at the Jülich Supercomputing Centre, and Associate Professor for High Performance Computing at the University of Bonn. Her expertise is in HPC system architecture and codesign. As leader of the DEEP project series, she has driven the development of the Modular Supercomputing Architecture, including the implementation and validation of hardware, software and applications. In addition, she has led the codesign efforts within the European Processor Initiative between 2018 and 2024. From 2024 to 2025, during a sabbatical year, she took the position of Senior Principal Solution Architect at SiPEARL. She holds a Master’s degree in Astrophysics from the University Complutense of Madrid (Spain) and a PhD in Physics from the University of Geneva (Switzerland).
Etienne Walter is a senior expert and project manager in the R&D Division of Eviden, an Atos business. He is currently coordinating, as General Manager, the phase 2 of the European Processor Initiative and contributes to the coordination of the EUPEX Pilot project.
Etienne studied computer science and graduated as an engineer at Supelec (now CentraleSupelec – part of Paris-Saclay University ). He worked as software engineer, team manager and project manager in the telecommunication domain before joining the R&D division of Bull, now part of the Atos/Eviden group. He has been involved in HPC and Big Data projects for a number of years and was the project coordinator of H2020 projects Mont-Blanc 3 and Mont-Blanc 2020, while contributing to the preparation of EPI project.
Dr. Lilia Zaourar is a CEA expert in co-design techniques for Computing Architectures at CEA LIST. She received an MS and PhD in Operational Research and Computer Science from the University Joseph Fourier, Grenoble, in 2007 and 2010, respectively. She developed various optimization algorithms for the design and test of integrated circuits. Then, she was a temporary teaching and research assistant at the SoC department in Computer Science PARIS 6 Laboratory, Sorbonne University, from 2010 to 2012. She was involved in developing optimization strategies for the resource-sharing problem to test embedded memories. She joined the CEA LIST in 2012 and has participated in various national, European, and industrial research projects on real-time mixed-criticality systems, optimization strategies of runtime software for heterogeneous HPC and microservers, and FPGA emulation.
She led Modelling and Simulation activities within the first phase of the European Processor Initiative (EPI) project. She is currently involved in the second phase of EPI on co-design and exploration. Her research interests cover combinatorial optimization and operational research techniques with a special focus on optimization problems for electronic design automation and high-performance embedded systems, as well as testing and security. She is the leader of the working group ” Optimized Integreted Circuit ” funded by the French institution CNRS. She has been a SAMOS, SC, PMBS, and CoDit technical programs member. She has served as General Chair for Hipeac/Rapido 2023, 2024, and General Chair of the 50th Euromicro DSD/SEAA 2024 conference. Since 2025, she is vice chair of the French chapter IEEE CEDA.
The European Processor Initiative held its first Forum on 9 and 10 October, 2024, in Barcelona, Spain.
EPI Forum gathered experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers who discussed and presented EPI’s achievements so far and future developments in the Initiative.
Agenda of the event that was held can be found here: EPI FORUM AGENDA,
while the presentations and materials are available in our repository here:
https://www.european-processor-initiative.eu/dissemination-material/epi-forum-in-barcelona/
EPI Forum organizing committee wishes to thank the sponsors, speakers and panelists listed below for participating and making it a successful event. Stay tuned for announcements of the second EPI Forum next year!
