The European Processor Initiative (EPI) is proud to announce the open-source release of VPSim, the Virtual Prototyping Simulator developed by CEA-List, used for early software-hardware co-validation and performance exploration of the European HPC processor. This will enable the establishment of a community of hardware and software designers dedicated to the European HPC ecosystem, which will accelerate design evaluation while preserving accuracy and software-hardware co-validation phases of next-generation HPC and edge systems.

Modern multi-processor systems-on-chip (MPSoCs) integrate thousands of cores, deep and heterogeneous memory hierarchies, and high-bandwidth interconnects that are tightly coupled to their physical environments. Designers must navigate the increasing complexity of MPSoC architectures and, to meet stringent requirements for energy efficiency, compactness, and performance, must account for software workloads early in the design process. To achieve these objectives, early design exploration is essential, supported by effective tools for modeling and simulating complex computing systems.

MPSoC simulation requires a careful balance between fidelity, execution speed, and modeling flexibility, especially in systems that integrate deep memory hierarchies and heterogeneous computing elements. VPSim addresses these challenges through a decoupled simulation methodology that separates CPU and memory hierarchy modeling, offering an optimal trade-off between accuracy and simulation speed.

Built around QEMU-based CPU models (Arm and RISC-V) and SystemC/TLM 2.0 modules, VPSim supports full software stacks—from BIOS and hypervisors to application workloads—enabling early software–hardware co-validation and performance evaluation. It also integrates with other simulators and modeling tools through FMI-based co-simulation, serving as a flexible digital twin for next-generation HPC and edge systems.

By releasing VPSim as open source, CEA-List aims to strengthen European collaboration in digital design and accelerate innovation in virtual prototyping, co-simulation, and design-space exploration. The open release will allow academic and industrial partners to extend the framework with new models and methodologies targeting emerging HPC architectures.

VPSim has been a key co-design tool in the development of Rhea, the European high-performance computing (HPC) processor led by SiPearl, in collaboration with CEA, Jülich Supercomputing Centre, and FORTH-ICS.

VPSim is available on GitHub:

https://github.com/CEA-LIST/vpsim-release

About EPI

The European Processor Initiative (EPI) is a project whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

The project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

 

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 30 partners from 10 European countries, with the goal of achieving Europe’s independence in HPC chip technologies and infrastructure, is nearing the finishing line, at the end of a two-stage run.

The project team will attend the Supercomputing 25, premier global event in the HPC and AI fields, to be held from November 16-21 in St. Louis, Missouri, USA. As a part of the EPI team at the booth #4410, Proactive Compute, a new spin-off  from University of Zagreb’s Faculty of Electrical Engineering and Computing (UNIZG-FER), will be ready to discuss and showcase two of its key IP’s FAUST and FEVER.

FAUST is a high-performance, pipelined floating-point unit (FPU) IP designed for integration into RISC-V cores with vector processing capabilities. Some key advantages of FAUST are:

Its advanced 2.0 version achieved significant area reduction while preserving a comprehensive feature set and full standards compliance. It has a configurable manual placement of pipeline registers to ensure an optimally segmented pipeline, eliminating the unpredictable and sub-optimal results from automatic retiming from synthesis tools.

FEVER, a UVM-based RISC-V FPU verification environment that complements FPU design. It is a SystemVerilog DPI wrapper which integrates FEVER into the UVM scoreboard to evaluate UUT’s outputs.

“We are thrilled to present FEVER and FAUST at SC25, marking a significant step forward in our mission to advance high-performance computing,” said Dr. Mario Kovač, Founder and CEO of Proactive Compute. “Designing and delivering advanced computational units to power the next generation of RISC-V processors has been both a complex and inspiring journey. FAUST, now silicon-proven and validated through several strategic EU-funded projects, exemplifies our commitment to innovation and technical excellence — and is now available for licensing from Proactive Compute.”

“The European Processor Initiative (EPI) proudly celebrates the launch of Proactive Compute, a company it helped bring to life. Through the FAUST and FEVER IPs now marketed by Proactive Compute, EPI continues to demonstrate not only its capacity for cutting-edge innovation but also its ability to translate technological breakthroughs into real-world impact. Together, EPI and Proactive Compute are reinforcing Europe’s leadership in high-performance computing (HPC) and AI processor technologies—guided by European values and committed to advancing the continent’s long-term strategic interests,” explains Eric Monchalin, Chair of the EPI Board.

For more comprehensive details about FAUST and FEVER, please visit Proactive Compute website http://www.proactivecompute.com/.

About EPI

The European Processor Initiative (EPI) is a project whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

The project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

The European Processor Initiative Co-Design Workshop, held on September 10-11 at FORTH (Heraklion, Greece), brought together leading Centres of Excellence (CoEs), research institutions, HPC companies, and hardware/software experts to advance Europe’s sovereignty in high-performance computing through collaborative hardware/software co-design. The workshop sessions showcased progress in adapting flagship scientific applications to emerging European processor technologies (with the Arm and RISC-V ISAs), integration of advanced memory hierarchies, and leveraging novel architectures such as chiplets and interposers. The workshop sessions, moderated by Etienne Walter (Eviden) and Manolis Marazakis (FORTH), included 2 keynotes, 20 technical presentations, and 2 panels.

Keynotes

Jesus Labarta (BSC), in his keynote on September 10 (Day-1), examined GPU-AI co-design through an HPC lens, emphasizing the value of combining microscopic-level analysis of computational kernel behavior together with macroscopic metrics for deep insights into performance. This approach is at the heart of tool-assisted co-design, and was showcased with the use of trace capture and analysis/visualization tools to reveal bottlenecks in large-scale AI workloads with the aim to guide RISC-V vectorization architectural optimizations.

Denis Dutoit (CEA-LETI), in his keynote on September 11 (Day-2), surveyed chiplet and interposer technology, highlighting their role in building complex systems through architectural disaggregation and packaging aggregation. Chiplets/interposers address energy-efficiency and scaling limits in HPC/embedded systems, and offer Europe a strategic opportunity to enhance computing autonomy via modular integration and a distributed supply chain.

Presentations of Day-1

Experiences and learnings from the EPAC test-chip were presented by Filippo Mantovani (BSC). The EPAC test-chip pairs a RISC-V scalar core with a long-vector VPU (supporting up to 16k-bit registers) for HPC efficiency. Hardware design tradeoffs have enabled high-throughput vector processing via multi-cycle execution. Co-design across compilers, libraries, and programming models (incl. auto-vectorization, pragmas, intrinsics) has been crucial for practical deployment.

The roadmap of the Rhea family of processors by SiPearl was presented by Craig Prunty (SiPearl). SiPearl advances European compute sovereignty by developing highly complex, energy-efficient Arm-based processors for HPC and AI. SiPearl positions its technology, exemplified by the upcoming deployment of Rhea processors in the JUPITER exascale system, as a key enabler for achieving high performance with superior energy efficiency.

RISC-V IP for bandwidth-intensive SoCs was presented by Jose-Maria Arnau (Semidynamics). Key innovations include “Gazzillion Misses” technology to mitigate memory latency and maximize bandwidth utilization, and tightly integrated out-of-order CPU cores with configurable Vector/Tensor Units for demanding AI and HPC workloads.

Experiences and perspectives from the EUPILOT project were presented by Carlos Puchol (BSC). The EUPILOT project aims to build a European accelerator platform using RISC-V technology to enhance HPC/AI supply-chain autonomy. Key innovations include modular hardware (EAM) with liquid-immersion cooling for energy efficiency, and extensive software porting/optimization for scientific workloads.

Codesign experiences in the EUPEX project were presented by Matteo Turisini (CINECA). The EUPEX project advances a European modular exascale supercomputer using ARM-based processors and software tools, prioritizing co-design with scientific applications. A primary focus in EUPEX has been the enablement of energy-efficient workflows via comprehensive toolchains.

RAS (Reliability, Availability, Serviceability) concerns were addressed in two presentations. Dimitris Gizopoulos (University of Athens) discussed Silent Data Corruptions (SDCs): unnoticed hardware faults causing incorrect outputs. SDCs are a critical reliability risk in large-scale computing. Even low per-CPU SDC rates (0.3–1 per 1000) translate to significant corrupted results at hyperscaler scale. Addressing SDCs requires a co-design approach across hardware and systems, following the pattern: Model, Measure, Detect, Mitigate.

Daniele Rossi (University of Pisa) described ENGAGE-V, a modular and RERI-compliant RAS IP for RISC-V systems, applicable across diverse application domains. Standardized error logging and reporting IP is crucial beyond just detection/correction (e.g. via ECC) to improve serviceability and availability. ENGAGE-V provides a flexible, lightweight solution for capturing error context and triggering targeted software recovery, complementing existing techniques.

Presentations of Day-2

Two presentations provided perspectives on Arm and GPU technologies, offering a view of the historical evolution from low-power ARM+GPU platforms to modern high-performance HPC accelerators, with attention to power envelopes and heterogeneous integration. Jean-Pierre Panzierra (Eviden & ETP4HPC) provided a personal account detailing Europe’s 15-year journey (2010–2025) to establish an Arm-based HPC ecosystem, driven by sovereignty concerns. Persistent collaboration across research (incl. the MontBlanc series of projects) and industry was essential to overcome hardware/software gaps. Despite vendor and market unpredictability, viable Arm HPC servers has been achieved through iterative refinement.

Filippo Spiga (NVIDIA) traced the evolution of Arm processors and GPU acceleration in HPC. Early prototypes like CARMA (2012) demonstrated the energy efficiency of Arm+GPU designs, paving the way for modern datacenter solutions. Industry momentum (e.g., Arm Neoverse, NVIDIA Grace) and software ecosystems (CUDA, Jetson) now enable co-designed, power-efficient HPC systems.

Paul Carpenter (BSC) presented an overview of the Digital Autonomy with RISC-V in Europe (DARE) project. The DARE project advances European HPC/AI sovereignty through a RISC‑V‑centric open stack, combining chiplet-based hardware (vector, AI, and general-purpose processors) and full software co-design. Key goals include energy-efficient exascale-ready silicon, AI-accelerated workloads, and prototypes enabling next-generation scientific computing. Among other innovations, DARE encompasses in-memory computing accelerators for robust AI and virtual/physical prototyping for rapid system validation.

Matteo Mascagni (EuroHPC JU) provided a personal interpretation of co-design, emphasizing upcoming daunting energy efficiency and sustainability challenges (especially for zettascale systems). He argued that current HPC practices often mislabel software tuning for off-the-shelf hardware as true “Hardware/Software Co-Design”, which instead requires coordinated development of both types of components. Sustainable zettascale demands true co-design, i.e. application-driven hardware/software collaboration prioritizing energy efficiency, heterogeneity, and data locality. Critical shifts include moving beyond CPU-centric models to accelerator-dominated architectures, mixed-precision computing, and Gustafson’s Law scalability.

Lluc Alvarez (BSC) presented an overview of the Barcelona Zettascale Lab project, which focuses on open RISC-V hardware co-design, targeting a high-performance multicore processor and vector accelerator. Key achievements include planned Intel Foundry tapeouts, a 150+ multidisciplinary team, and contributions to EU initiatives like EPI.

Vassilis Papaefstahiou (FORTH) presented a retrospective on the evolution of RISC‑V EPI prototypes, with emphasis on the memory hierarchy and tiled architecture, and highlighting two central design decisions: (1) Adoption of AMBA5 CHI coherence with distributed non-blocking L2/LLC slices for high-bandwidth vector/ML workloads and (2) Strategic use of FPGA bridging via C2C links for early validation and I/O, enabling practical silicon bring-up across multiple tape-outs.

Mario Kovač (University of Zagreb) presented FAUST, a highly configurable FPU for RISC-V vector processors, compliant with IEEE 754-2019 and RVV v1.0. Key features include extensive operation support (FMA, division, conversions) and flexible pipeline tuning. FAUST 2.0 significantly reduces area through manual register placement and algorithm choices while maintaining performance and standards compliance.

Sylvie Lesmanne (Eviden) and Denis Dutoit (CEA-LETI), with contributions by Anthony Philippe (CEA-LETI) and Romain Dolbeau (SiPearl), presented the EPI Common Platform, a system architecture blueprint for processors and accelerators that prioritizes vendor neutrality and performance efficiency. The EPI Common Platform relies on two pillars: (1) A software platform leveraging open standards (MPI, OpenMP, SYCL) to enable portable hybrid programming across diverse hardware, and (2) A hardware platform adopting chiplet-based designs and global D2D standards (specifically UCIe) for scalable, interoperable systems.

Panels

The panel on Day-1 examined technology challenges and opportunities for European chips. Starting from the technical points raised during the presentation of the EPI Common Platform, the panel also considered challenges due to the organizational complexity of large-scale projects and the difficulty in establishing trust in a market context. Other challenges discussed include access to the latest EDA tools, and access to funding in relatively short timeframes. The concept of mission-specific HPC was also discussed, as a co-design path distinct of general-purpose computing, as a way to address power consumption and cooling challenges at extreme scales.

The theme of the panel on Day-2 was how to apply codesign to meet future needs of the European HPC ecosystem. Five ongoing CoEs presented summaries of their work in adapting and optimizing domain-specific codes for exascale systems.

Plasma-PEPSC focuses on flagship plasma simulation codes (BIT1, GENE, PIConGPU, Vlasiator) for fusion energy, plasma accelerators, and space physics. Optimization strategies include SVE/NEON vectorization, cache locality improvements, and precision reduction, tested on Arm-based Rhea platforms.

SPACE develops scalable astrophysical simulation codes, assessing ARM readiness, SIMD vectorization impacts, energy tuning, and HBM relevancy for performance gains.

MaX3 targets materials science applications (Quantum ESPRESSO, Yambo, BigDFT, FLEUR, Siesta) with studies on HBM vs DDR performance, fine-grained object-level HBM placement, and vectorization improvements across architectures.

ESiWACE3 focuses on Weather and climate simulation workloads explored on ARM and RISC-V platforms, demonstrating RVV-based vectorization on real hardware and highlighting ARM maturity and potential for RISC-V in HPC.

ChEESE2P models solid earth phenomena (seismic waves, volcanology, tsunami) using mini-apps to study ARM+HBM and RISC-V accelerator integration, emphasizing memory bandwidth’s critical role.

Conclusion

Overall, the workshop provided a comprehensive overview of how the European Processor Initiative is contributing to create a sustainable and sovereign European HPC ecosystem, by co-developing processors, accelerators, and software stacks tailored to the needs of strategic scientific domains. Through iterative co-design cycles, domain specialists and hardware designers work together to realize exascale-ready applications, ensuring that Europe remains competitive in global HPC innovation and maintains control over critical computational technologies.

Materials are available in our dissemination and communication repository: https://www.european-processor-initiative.eu/dissemination-material/codesign-workshop-in-heraklion/

The European Processor Initiative (EPI), a project with 27 partners from 10 European countries, driving EU independence in HPC chip technologies and HPC infrastructure is proud to announce its Forum to be held in Paris, France, October 6-7, 2025.

Why attend?

After last year’s successful Forum opening, the largest project spearheading European efforts to power exascale supercomputers with sovereignty, resilience, and confidence, is inviting the leading voices from academia, industry, and the HPC ecosystem to continue to discuss progress, results and ways ahead for European leadership in HPC and AI processor, and accelerator technologies.

The main theme of discussion will be European technologies for true digital and AI freedom:

Attendees are expected to hear keynotes from industry leaders and champions in the field: Dr. Marc Duranton from CEA, Carlo Cavazzoni from Leonardo, Prof. David Atienza from EPFL, industry views from Platinum EPI Forum sponsors DDN and Eviden, and Gold EPI Forum sponsors: AMD, CEA, E4 and SiPearl.

Three technical sessions will be held related to Codesign efforts in EPI, Arm/Rhea and RISC-V in EPI. Both days of agenda also include panel discussions – one on European sovereignty in HPC, Edge and AI and another on Making the convergence between Cloud, HPC, AI and Edge.

EPI invites you to take part in this event, with EPI researchers, engineers, stakeholders and global technology providers from all over the globe, shaping the future of HPC!

Registration

Registration is open at the EPI website: https://epiforum-registration.site.digitevent.com/page/informations/, and all other details regarding the event and policies are available on our website here: https://www.european-processor-initiative.eu/epi-forum-2025/.

Venue

EPI Forum will be held in magnificent Paris, at the L’Hôtel des Arts & Métiers, 9bis Avenue d’Iéna, 75016 Paris, France. The Forum will be organized in two days: the event starts on Oct 6 in the afternoon and continues Oct 7.

We look forward to seeing you at the EPI Forum!

Forum sponsors 

EuroHPC Joint Undertaking (EuroHPC JU) Summit took place in Krakow, Poland, from 18 to 20 March, 2025. EPI Representatives attended several sessions and poster session, including the Fish (&Chips) Bowl: Future Microprocessor Architectures, featuring our General Manager, Etienne Walter and on a panel called Future Technologies Powering the Current and Upcoming European Supercomputing Infrastructure: Road to EU sovereignty, featuring several EPI scientists and our programme manager, Alexandra Kourfali.

Jean Pierre Panziera, HPC Chief Technology director at Eviden, also attended the panel and announced the dates of the second edition of the European Processor Initiative Forum – 6 and 7 October, 2025 in Paris.

In addition to panel and discussion participation, our colleagues from BSC also used the lab space to demonstrate our EPAC accelerator, while our Chief Communication Officer, prof. dr. sc. Mario Kovač, attended the poster session with EPI poster.

Fish (&Chips) Bowl: Future Microprocessor Architectures Panel

From January 20 to 23, HiPEAC25 took place Palau de Congressos de Barcelona in Barcelona, Spain. Our team from BSC and FORTH was at the booth #21, answering questions about the road so far in the European Processor Initiative and showcasing EPAC – European Processor Accelerator demo.

In addition to that, colleagues from E4 Computer Engineering SpA and Barcelona Supercomputing Center organized a workshop titled “RISC-V: the cornerstone ISA for the next generation of HPC infrastructures”. There, our colleague from BSC, Pablo Vizcaino, presented his paper titled “RAVE: The RISC-V Analyzer of Vector Executions”.

Alexandra Kourfali from EuroHPC Joint Undertaking (EuroHPC JU) gave an overview of EuroHPC RISC-V initiatives.

Marta Garcia-Gasulla from BSC also attended a workshop organized by Centers of Excellence, where she gave a talk titled “Co-design, from a buzzword to a reality, an EPI success story”. She explained a very high overview of the different architectures being developed at EPI, an explanation of what the SDVs (Software Development Vehicles) are and how they can be used to co-design applications, system software and hardware. She also talked about the success story of a collaboration between EPI and the CEEC Center of Excellence, where she and her colleagues optimized a CFD code for the EPAC accelerator using the SDVs.

Marta Garcia-Gasulla at HiPEAC workshop

The presentations are available here, in our dissemination repository.

EPI, EUPILOT and EUPEX are joining forces at the Supercomputing24 conference, which is taking place in Atlanta, Georgia, USA, from November 17 – 22, 2024. The three projects will showcase their latest results and ideas at booth #4043.

AT THE BOOTH

Demo Pod

Filippo Mantovani and Pablo Vizcaino Serrano will present EPI’s and EUPILOT’s EPAC prototype featuring a RISC-V vector processing unit developed at the Barcelona Supercomputing Center (BSC). Schedule:

Tuesday, 19 November, 11:00 to 12:00pm EST
Wednesday, 20 November, 11:00 to 12:00pm EST
Thursday, 21 November, 13:00 to 14:00pm EST

Discussions

Researchers and representatives from various EPI consortium members will greet you at the booth to discuss the latest news in EPI development.

Specifically, the joint booth will organize a hot topic Question of the Day for Tuesday and Wednesday. The agenda is as follows:

Tuesday – November 19, 2024, 3:00-4:00pm EST

TOPIC: What are the competitive advantages of Rhea1, SiPearl’s processor, designed as part of the EPI project? Participation link https://www.menti.com/al9zdpz6fbza

Wednesday – November 20, 2024, 3:00-4:00pm EST

TOPIC: What do you think is the biggest challenge for widespread adoption of RISC-V in the area of HPC? Participation link https://www.menti.com/als6c1a31r8a

Questions are open for voting already! Scan the QR code, or follow the link and share your opinion, regardless of whether you are attending SC24 (1-minute poll). If you are joining us at SC24 in person, come round to booth 4043 for live results and an engaging discussion on both day!

Program

Among other fascinating talks at SC24, EPI researchers will also take part in the workshops and symposiums. Make sure to catch it:

European HPC Passport Stamp Collection!

Take a European HPC passport and go! Here’s how it works:

EuroHPC JU, LUMI/CSC, SiPearl, IT4Innovations, CIDS@TU Dresden, EPI/EUPILOT/EUPEX, ETP4HPC, PRACE, BSC, LRZ, HLRS, JSC, and CSCS/ETH Zürich.

Collect, connect, and celebrate European HPC! Good luck and happy stamping!

On October 9 and 10, 2024, the European Processor Initiative organized and hosted its first EPI Forum in Barcelona, Spain.

The event was organized as a two-day conference, followed by an afternoon event organized by EUPEX project. More than 100 people attended the EPI Forum and participated in lively discussions, presentations and two panels.

The event was sponsored by six global technology providers: platinum sponsors included Arm, Eviden and NVIDIA, while AMD, Semidynamics and SiPearl were gold sponsors of the event.

After an introduction by Chairman of EPI Board, Eric Moncahlin, and a general overview of EPI given by project General Manager, Etienne Walter, the first day was opened by keynotes from notable speakers.

Director of BSC, Mateo Valero, spoke about the situation in Europe and the reasons for Buy versus Build when it comes to supercomputers, making a case for European sovereignty, and Stéphane Requena, CTO from GENCI, gave an insightful presentation about AI in Europe and infrastructure requirements, French ecosystem and GENCI’s work in the field.

The day continued with speeches from technology providers – Jean-Pierre Panziera from Eviden talked about HPC in the AI era, Eric Lalardie from Arm discussed Arm’s European activities and enabling European innovation, Daniele Piccarozzi from AMD presented his company’s solutions for HPC and AI, Philippe Notton, CEO of SiPearl, unveiled information about SiPearl’s Seine platform, while Roger Espasa, CEO of Semidynamics, gave a RISC-V-based perspective of his company’s All-in-One solutions for RISC-V AI.

The end of the first day was reserved for Arm and Rhea in high-end HPC, so EPI’s board member and SiPearl’s VP, Craig Prunty, gave an exhaustive presentation regarding key features of Rhea, GPP technology and exascale system for EPI. Following his view, Eric Monchalin introduced the end-day panel and panelists of the first day: Eric Lalardie, Jean-Pierre Panziera, Filippo Spiga from NVIDIA, Roger Espasa, Craig Prunty, Daniele Piccarozzi, Alexandra Kourfali from EuroHPC JU, and Etienne Walter. The group talked about the opportunities and risks in HPC ecosystem presented by the fact that innovation is driven with market demands which shifted towards cloud and AI, discussions about the importance of end-to-end co-design, costs of chip design, European sovereignty, and the ever-present need for sustainability and net-zero emissions.

The second day was opened by a keynote speaker from EuroHPC JU, Alenxandra Kourfali, who gave an interesting presentation on EuroHPC activities, chips initiatives, and the positioning of EPI in this environment. Her presentation was followed by NVIDIA’s take delivered by Rod Evans, who talked about the interesting concept of enabling development of AI in nations. The following segment was dedicated to RISC-V activities in EPI – and the EPI accelerator EPAC. Filippo Mantovani from BSC, EPI’s stream leader, gave an overview of EPAC and VEC, while Andrea Bocco from CEA and Tim Fischer from ETHZ talked about the variable extended precision accelerator for scientific computing applications and the Snitch core. David Snelling from Fujitsu gave a talk about Arm processor MONAKA in Fujitsu.

The day and the Forum closed with a panel on RISC-V future. It was moderated by Etienne Walter, EPI’s General Manager, and the panelists – Jean-Pierre Panziera, Daniele Gregori from E4, Manolis Marazakis from FORTH, Fabrizio Gagliardi from BSC, Alexandra Kourfalis Osman Unsal from BSC and Eric Monchalin, EPI’s Chairman of the Board – discussed about performance and scalability and how RISC-V compares to existing architectures like ARM, x86, etc., both now and in some predictions for the future. The panel also talked about the software ecosystem and whether the current one is mature enough to support large-scale HPC deployment on RISC-V. Panellists also offered their views on how the open-source nature of RISC-V would ensure standardization and avoid fragmentation in HPC implementations, ideas on cost and economic viability, energy efficiency and sustainability and IP issues – which relates to Europe’s strive for sovereignty.

The event was followed by EUPEX Forum presentations, which were open to all EPI Forum attendees to listen to free of charge.

All EPI Forum presentations are available in our repository here: https://www.european-processor-initiative.eu/dissemination-material/epi-forum-in-barcelona/, while highlight videos from presentations will be published on EPI YT channel here: https://www.youtube.com/@EuropeanProcessorInitiative.

Next year’s Forum will be held in Paris, stay tuned for more info!

The European Processor Initiative (EPI), a project with 27 partners from 10 European countries, with the goal of helping to achieve EU independence in HPC chip technologies and HPC infrastructure is proud to announce the first EPI Forum to be held in Barcelona, Spain, October 9-10, 2024.

Why attend?

For the first time, the largest project spearheading European efforts to power exascale supercomputers is inviting experts to meet and discuss progress, results and ways ahead for the European exascale processors and accelerators.

Attendees are expected to hear keynotes from industry leaders and champions in the field, keynote on AI by GENCI, keynote on Supercomputing by BSC and a keynote on the HPC future by EuroHPC as well as industry views from Platinum EPI Forum sponsors: Arm, Eviden, NVIDIA, and Gold EPI Forum sponsors: AMD, Semidynamics and SiPearl.

Forum will present an overview of EPI achievements and future plans including Rhea GPP, RISC-V based EPI accelerator cores and various applications. Each day will conclude with a panel discussion with distinguished panellists giving boarder views on presented topics.

EPI invites you to take part in this event, with EPI experts and global technology providers from all over the globe, shaping the future of HPC!

Registration

Registration is open at the EPI website: https://buy.stripe.com/14k3dz0OH9t40us9AA, and all other details regarding the event and policies are available on our website here: https://www.european-processor-initiative.eu/epi-forum-2024/

Venue

EPI Forum will be held in beautiful Barcelona, at the Barceló Sants hotel. The Forum will be organized in two days: the event starts on Oct 9 in the afternoon and continues with morning sessions on Oct 10. In the afternoon of Oct 10, our colleagues from EUPEX project will continue with their event at the same venue, which you can find out more about here: https://eupex.eu/events/eupex-forum-at-the-epi-forum/

We look forward to seeing you at the EPI Forum!

 

The 2024 edition of the ACM Summer School on HPC Architectures for AI and Dedicated Applications, organized by The Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC), will take place in Barcelona from 2-6 September 2024. This year’s program focuses on the convergence between HPC and AI, and it will also explore emerging research areas such as Quantum Computing. The school targets PhD and recent postdocs in HPC and AI. Exceptionally, outstanding MSc students with proven interest and/or experience in projects related to HPC and/or AI are also accepted. Participation in the school is free of charge. Sixty accepted participants will spend one week in Barcelona, attending formal lectures, invited talks, and other activities. The school will cover accommodation expenses and catering during school hours.
More information: https://europe.acm.org/seasonal-schools/hpc/2024

Copyright 2022 All Right Resereved

This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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