The European Processor Initiative Co-Design Workshop, held on September 10-11 at FORTH (Heraklion, Greece), brought together leading Centres of Excellence (CoEs), research institutions, HPC companies, and hardware/software experts to advance Europe’s sovereignty in high-performance computing through collaborative hardware/software co-design. The workshop sessions showcased progress in adapting flagship scientific applications to emerging European processor technologies (with the Arm and RISC-V ISAs), integration of advanced memory hierarchies, and leveraging novel architectures such as chiplets and interposers. The workshop sessions, moderated by Etienne Walter (Eviden) and Manolis Marazakis (FORTH), included 2 keynotes, 20 technical presentations, and 2 panels.

Keynotes

Jesus Labarta (BSC), in his keynote on September 10 (Day-1), examined GPU-AI co-design through an HPC lens, emphasizing the value of combining microscopic-level analysis of computational kernel behavior together with macroscopic metrics for deep insights into performance. This approach is at the heart of tool-assisted co-design, and was showcased with the use of trace capture and analysis/visualization tools to reveal bottlenecks in large-scale AI workloads with the aim to guide RISC-V vectorization architectural optimizations.

Denis Dutoit (CEA-LETI), in his keynote on September 11 (Day-2), surveyed chiplet and interposer technology, highlighting their role in building complex systems through architectural disaggregation and packaging aggregation. Chiplets/interposers address energy-efficiency and scaling limits in HPC/embedded systems, and offer Europe a strategic opportunity to enhance computing autonomy via modular integration and a distributed supply chain.

Presentations of Day-1

Experiences and learnings from the EPAC test-chip were presented by Filippo Mantovani (BSC). The EPAC test-chip pairs a RISC-V scalar core with a long-vector VPU (supporting up to 16k-bit registers) for HPC efficiency. Hardware design tradeoffs have enabled high-throughput vector processing via multi-cycle execution. Co-design across compilers, libraries, and programming models (incl. auto-vectorization, pragmas, intrinsics) has been crucial for practical deployment.

The roadmap of the Rhea family of processors by SiPearl was presented by Craig Prunty (SiPearl). SiPearl advances European compute sovereignty by developing highly complex, energy-efficient Arm-based processors for HPC and AI. SiPearl positions its technology, exemplified by the upcoming deployment of Rhea processors in the JUPITER exascale system, as a key enabler for achieving high performance with superior energy efficiency.

RISC-V IP for bandwidth-intensive SoCs was presented by Jose-Maria Arnau (Semidynamics). Key innovations include “Gazzillion Misses” technology to mitigate memory latency and maximize bandwidth utilization, and tightly integrated out-of-order CPU cores with configurable Vector/Tensor Units for demanding AI and HPC workloads.

Experiences and perspectives from the EUPILOT project were presented by Carlos Puchol (BSC). The EUPILOT project aims to build a European accelerator platform using RISC-V technology to enhance HPC/AI supply-chain autonomy. Key innovations include modular hardware (EAM) with liquid-immersion cooling for energy efficiency, and extensive software porting/optimization for scientific workloads.

Codesign experiences in the EUPEX project were presented by Matteo Turisini (CINECA). The EUPEX project advances a European modular exascale supercomputer using ARM-based processors and software tools, prioritizing co-design with scientific applications. A primary focus in EUPEX has been the enablement of energy-efficient workflows via comprehensive toolchains.

RAS (Reliability, Availability, Serviceability) concerns were addressed in two presentations. Dimitris Gizopoulos (University of Athens) discussed Silent Data Corruptions (SDCs): unnoticed hardware faults causing incorrect outputs. SDCs are a critical reliability risk in large-scale computing. Even low per-CPU SDC rates (0.3–1 per 1000) translate to significant corrupted results at hyperscaler scale. Addressing SDCs requires a co-design approach across hardware and systems, following the pattern: Model, Measure, Detect, Mitigate.

Daniele Rossi (University of Pisa) described ENGAGE-V, a modular and RERI-compliant RAS IP for RISC-V systems, applicable across diverse application domains. Standardized error logging and reporting IP is crucial beyond just detection/correction (e.g. via ECC) to improve serviceability and availability. ENGAGE-V provides a flexible, lightweight solution for capturing error context and triggering targeted software recovery, complementing existing techniques.

Presentations of Day-2

Two presentations provided perspectives on Arm and GPU technologies, offering a view of the historical evolution from low-power ARM+GPU platforms to modern high-performance HPC accelerators, with attention to power envelopes and heterogeneous integration. Jean-Pierre Panzierra (Eviden & ETP4HPC) provided a personal account detailing Europe’s 15-year journey (2010–2025) to establish an Arm-based HPC ecosystem, driven by sovereignty concerns. Persistent collaboration across research (incl. the MontBlanc series of projects) and industry was essential to overcome hardware/software gaps. Despite vendor and market unpredictability, viable Arm HPC servers has been achieved through iterative refinement.

Filippo Spiga (NVIDIA) traced the evolution of Arm processors and GPU acceleration in HPC. Early prototypes like CARMA (2012) demonstrated the energy efficiency of Arm+GPU designs, paving the way for modern datacenter solutions. Industry momentum (e.g., Arm Neoverse, NVIDIA Grace) and software ecosystems (CUDA, Jetson) now enable co-designed, power-efficient HPC systems.

Paul Carpenter (BSC) presented an overview of the Digital Autonomy with RISC-V in Europe (DARE) project. The DARE project advances European HPC/AI sovereignty through a RISC‑V‑centric open stack, combining chiplet-based hardware (vector, AI, and general-purpose processors) and full software co-design. Key goals include energy-efficient exascale-ready silicon, AI-accelerated workloads, and prototypes enabling next-generation scientific computing. Among other innovations, DARE encompasses in-memory computing accelerators for robust AI and virtual/physical prototyping for rapid system validation.

Matteo Mascagni (EuroHPC JU) provided a personal interpretation of co-design, emphasizing upcoming daunting energy efficiency and sustainability challenges (especially for zettascale systems). He argued that current HPC practices often mislabel software tuning for off-the-shelf hardware as true “Hardware/Software Co-Design”, which instead requires coordinated development of both types of components. Sustainable zettascale demands true co-design, i.e. application-driven hardware/software collaboration prioritizing energy efficiency, heterogeneity, and data locality. Critical shifts include moving beyond CPU-centric models to accelerator-dominated architectures, mixed-precision computing, and Gustafson’s Law scalability.

Lluc Alvarez (BSC) presented an overview of the Barcelona Zettascale Lab project, which focuses on open RISC-V hardware co-design, targeting a high-performance multicore processor and vector accelerator. Key achievements include planned Intel Foundry tapeouts, a 150+ multidisciplinary team, and contributions to EU initiatives like EPI.

Vassilis Papaefstahiou (FORTH) presented a retrospective on the evolution of RISC‑V EPI prototypes, with emphasis on the memory hierarchy and tiled architecture, and highlighting two central design decisions: (1) Adoption of AMBA5 CHI coherence with distributed non-blocking L2/LLC slices for high-bandwidth vector/ML workloads and (2) Strategic use of FPGA bridging via C2C links for early validation and I/O, enabling practical silicon bring-up across multiple tape-outs.

Mario Kovač (University of Zagreb) presented FAUST, a highly configurable FPU for RISC-V vector processors, compliant with IEEE 754-2019 and RVV v1.0. Key features include extensive operation support (FMA, division, conversions) and flexible pipeline tuning. FAUST 2.0 significantly reduces area through manual register placement and algorithm choices while maintaining performance and standards compliance.

Sylvie Lesmanne (Eviden) and Denis Dutoit (CEA-LETI), with contributions by Anthony Philippe (CEA-LETI) and Romain Dolbeau (SiPearl), presented the EPI Common Platform, a system architecture blueprint for processors and accelerators that prioritizes vendor neutrality and performance efficiency. The EPI Common Platform relies on two pillars: (1) A software platform leveraging open standards (MPI, OpenMP, SYCL) to enable portable hybrid programming across diverse hardware, and (2) A hardware platform adopting chiplet-based designs and global D2D standards (specifically UCIe) for scalable, interoperable systems.

Panels

The panel on Day-1 examined technology challenges and opportunities for European chips. Starting from the technical points raised during the presentation of the EPI Common Platform, the panel also considered challenges due to the organizational complexity of large-scale projects and the difficulty in establishing trust in a market context. Other challenges discussed include access to the latest EDA tools, and access to funding in relatively short timeframes. The concept of mission-specific HPC was also discussed, as a co-design path distinct of general-purpose computing, as a way to address power consumption and cooling challenges at extreme scales.

The theme of the panel on Day-2 was how to apply codesign to meet future needs of the European HPC ecosystem. Five ongoing CoEs presented summaries of their work in adapting and optimizing domain-specific codes for exascale systems.

Plasma-PEPSC focuses on flagship plasma simulation codes (BIT1, GENE, PIConGPU, Vlasiator) for fusion energy, plasma accelerators, and space physics. Optimization strategies include SVE/NEON vectorization, cache locality improvements, and precision reduction, tested on Arm-based Rhea platforms.

SPACE develops scalable astrophysical simulation codes, assessing ARM readiness, SIMD vectorization impacts, energy tuning, and HBM relevancy for performance gains.

MaX3 targets materials science applications (Quantum ESPRESSO, Yambo, BigDFT, FLEUR, Siesta) with studies on HBM vs DDR performance, fine-grained object-level HBM placement, and vectorization improvements across architectures.

ESiWACE3 focuses on Weather and climate simulation workloads explored on ARM and RISC-V platforms, demonstrating RVV-based vectorization on real hardware and highlighting ARM maturity and potential for RISC-V in HPC.

ChEESE2P models solid earth phenomena (seismic waves, volcanology, tsunami) using mini-apps to study ARM+HBM and RISC-V accelerator integration, emphasizing memory bandwidth’s critical role.

Conclusion

Overall, the workshop provided a comprehensive overview of how the European Processor Initiative is contributing to create a sustainable and sovereign European HPC ecosystem, by co-developing processors, accelerators, and software stacks tailored to the needs of strategic scientific domains. Through iterative co-design cycles, domain specialists and hardware designers work together to realize exascale-ready applications, ensuring that Europe remains competitive in global HPC innovation and maintains control over critical computational technologies.

Materials are available in our dissemination and communication repository: https://www.european-processor-initiative.eu/dissemination-material/codesign-workshop-in-heraklion/

The European Processor Initiative (EPI), a project with 27 partners from 10 European countries, driving EU independence in HPC chip technologies and HPC infrastructure is proud to announce its Forum to be held in Paris, France, October 6-7, 2025.

Why attend?

After last year’s successful Forum opening, the largest project spearheading European efforts to power exascale supercomputers with sovereignty, resilience, and confidence, is inviting the leading voices from academia, industry, and the HPC ecosystem to continue to discuss progress, results and ways ahead for European leadership in HPC and AI processor, and accelerator technologies.

The main theme of discussion will be European technologies for true digital and AI freedom:

Attendees are expected to hear keynotes from industry leaders and champions in the field: Dr. Marc Duranton from CEA, Carlo Cavazzoni from Leonardo, Prof. David Atienza from EPFL, industry views from Platinum EPI Forum sponsors DDN and Eviden, and Gold EPI Forum sponsors: AMD, CEA, E4 and SiPearl.

Three technical sessions will be held related to Codesign efforts in EPI, Arm/Rhea and RISC-V in EPI. Both days of agenda also include panel discussions – one on European sovereignty in HPC, Edge and AI and another on Making the convergence between Cloud, HPC, AI and Edge.

EPI invites you to take part in this event, with EPI researchers, engineers, stakeholders and global technology providers from all over the globe, shaping the future of HPC!

Registration

Registration is open at the EPI website: https://epiforum-registration.site.digitevent.com/page/informations/, and all other details regarding the event and policies are available on our website here: https://www.european-processor-initiative.eu/epi-forum-2025/.

Venue

EPI Forum will be held in magnificent Paris, at the L’Hôtel des Arts & Métiers, 9bis Avenue d’Iéna, 75016 Paris, France. The Forum will be organized in two days: the event starts on Oct 6 in the afternoon and continues Oct 7.

We look forward to seeing you at the EPI Forum!

Forum sponsors 

EuroHPC Joint Undertaking (EuroHPC JU) Summit took place in Krakow, Poland, from 18 to 20 March, 2025. EPI Representatives attended several sessions and poster session, including the Fish (&Chips) Bowl: Future Microprocessor Architectures, featuring our General Manager, Etienne Walter and on a panel called Future Technologies Powering the Current and Upcoming European Supercomputing Infrastructure: Road to EU sovereignty, featuring several EPI scientists and our programme manager, Alexandra Kourfali.

Jean Pierre Panziera, HPC Chief Technology director at Eviden, also attended the panel and announced the dates of the second edition of the European Processor Initiative Forum – 6 and 7 October, 2025 in Paris.

In addition to panel and discussion participation, our colleagues from BSC also used the lab space to demonstrate our EPAC accelerator, while our Chief Communication Officer, prof. dr. sc. Mario Kovač, attended the poster session with EPI poster.

Fish (&Chips) Bowl: Future Microprocessor Architectures Panel

From January 20 to 23, HiPEAC25 took place Palau de Congressos de Barcelona in Barcelona, Spain. Our team from BSC and FORTH was at the booth #21, answering questions about the road so far in the European Processor Initiative and showcasing EPAC – European Processor Accelerator demo.

In addition to that, colleagues from E4 Computer Engineering SpA and Barcelona Supercomputing Center organized a workshop titled “RISC-V: the cornerstone ISA for the next generation of HPC infrastructures”. There, our colleague from BSC, Pablo Vizcaino, presented his paper titled “RAVE: The RISC-V Analyzer of Vector Executions”.

Alexandra Kourfali from EuroHPC Joint Undertaking (EuroHPC JU) gave an overview of EuroHPC RISC-V initiatives.

Marta Garcia-Gasulla from BSC also attended a workshop organized by Centers of Excellence, where she gave a talk titled “Co-design, from a buzzword to a reality, an EPI success story”. She explained a very high overview of the different architectures being developed at EPI, an explanation of what the SDVs (Software Development Vehicles) are and how they can be used to co-design applications, system software and hardware. She also talked about the success story of a collaboration between EPI and the CEEC Center of Excellence, where she and her colleagues optimized a CFD code for the EPAC accelerator using the SDVs.

Marta Garcia-Gasulla at HiPEAC workshop

The presentations are available here, in our dissemination repository.

EPI, EUPILOT and EUPEX are joining forces at the Supercomputing24 conference, which is taking place in Atlanta, Georgia, USA, from November 17 – 22, 2024. The three projects will showcase their latest results and ideas at booth #4043.

AT THE BOOTH

Demo Pod

Filippo Mantovani and Pablo Vizcaino Serrano will present EPI’s and EUPILOT’s EPAC prototype featuring a RISC-V vector processing unit developed at the Barcelona Supercomputing Center (BSC). Schedule:

Tuesday, 19 November, 11:00 to 12:00pm EST
Wednesday, 20 November, 11:00 to 12:00pm EST
Thursday, 21 November, 13:00 to 14:00pm EST

Discussions

Researchers and representatives from various EPI consortium members will greet you at the booth to discuss the latest news in EPI development.

Specifically, the joint booth will organize a hot topic Question of the Day for Tuesday and Wednesday. The agenda is as follows:

Tuesday – November 19, 2024, 3:00-4:00pm EST

TOPIC: What are the competitive advantages of Rhea1, SiPearl’s processor, designed as part of the EPI project? Participation link https://www.menti.com/al9zdpz6fbza

Wednesday – November 20, 2024, 3:00-4:00pm EST

TOPIC: What do you think is the biggest challenge for widespread adoption of RISC-V in the area of HPC? Participation link https://www.menti.com/als6c1a31r8a

Questions are open for voting already! Scan the QR code, or follow the link and share your opinion, regardless of whether you are attending SC24 (1-minute poll). If you are joining us at SC24 in person, come round to booth 4043 for live results and an engaging discussion on both day!

Program

Among other fascinating talks at SC24, EPI researchers will also take part in the workshops and symposiums. Make sure to catch it:

European HPC Passport Stamp Collection!

Take a European HPC passport and go! Here’s how it works:

EuroHPC JU, LUMI/CSC, SiPearl, IT4Innovations, CIDS@TU Dresden, EPI/EUPILOT/EUPEX, ETP4HPC, PRACE, BSC, LRZ, HLRS, JSC, and CSCS/ETH Zürich.

Collect, connect, and celebrate European HPC! Good luck and happy stamping!

On October 9 and 10, 2024, the European Processor Initiative organized and hosted its first EPI Forum in Barcelona, Spain.

The event was organized as a two-day conference, followed by an afternoon event organized by EUPEX project. More than 100 people attended the EPI Forum and participated in lively discussions, presentations and two panels.

The event was sponsored by six global technology providers: platinum sponsors included Arm, Eviden and NVIDIA, while AMD, Semidynamics and SiPearl were gold sponsors of the event.

After an introduction by Chairman of EPI Board, Eric Moncahlin, and a general overview of EPI given by project General Manager, Etienne Walter, the first day was opened by keynotes from notable speakers.

Director of BSC, Mateo Valero, spoke about the situation in Europe and the reasons for Buy versus Build when it comes to supercomputers, making a case for European sovereignty, and Stéphane Requena, CTO from GENCI, gave an insightful presentation about AI in Europe and infrastructure requirements, French ecosystem and GENCI’s work in the field.

The day continued with speeches from technology providers – Jean-Pierre Panziera from Eviden talked about HPC in the AI era, Eric Lalardie from Arm discussed Arm’s European activities and enabling European innovation, Daniele Piccarozzi from AMD presented his company’s solutions for HPC and AI, Philippe Notton, CEO of SiPearl, unveiled information about SiPearl’s Seine platform, while Roger Espasa, CEO of Semidynamics, gave a RISC-V-based perspective of his company’s All-in-One solutions for RISC-V AI.

The end of the first day was reserved for Arm and Rhea in high-end HPC, so EPI’s board member and SiPearl’s VP, Craig Prunty, gave an exhaustive presentation regarding key features of Rhea, GPP technology and exascale system for EPI. Following his view, Eric Monchalin introduced the end-day panel and panelists of the first day: Eric Lalardie, Jean-Pierre Panziera, Filippo Spiga from NVIDIA, Roger Espasa, Craig Prunty, Daniele Piccarozzi, Alexandra Kourfali from EuroHPC JU, and Etienne Walter. The group talked about the opportunities and risks in HPC ecosystem presented by the fact that innovation is driven with market demands which shifted towards cloud and AI, discussions about the importance of end-to-end co-design, costs of chip design, European sovereignty, and the ever-present need for sustainability and net-zero emissions.

The second day was opened by a keynote speaker from EuroHPC JU, Alenxandra Kourfali, who gave an interesting presentation on EuroHPC activities, chips initiatives, and the positioning of EPI in this environment. Her presentation was followed by NVIDIA’s take delivered by Rod Evans, who talked about the interesting concept of enabling development of AI in nations. The following segment was dedicated to RISC-V activities in EPI – and the EPI accelerator EPAC. Filippo Mantovani from BSC, EPI’s stream leader, gave an overview of EPAC and VEC, while Andrea Bocco from CEA and Tim Fischer from ETHZ talked about the variable extended precision accelerator for scientific computing applications and the Snitch core. David Snelling from Fujitsu gave a talk about Arm processor MONAKA in Fujitsu.

The day and the Forum closed with a panel on RISC-V future. It was moderated by Etienne Walter, EPI’s General Manager, and the panelists – Jean-Pierre Panziera, Daniele Gregori from E4, Manolis Marazakis from FORTH, Fabrizio Gagliardi from BSC, Alexandra Kourfalis Osman Unsal from BSC and Eric Monchalin, EPI’s Chairman of the Board – discussed about performance and scalability and how RISC-V compares to existing architectures like ARM, x86, etc., both now and in some predictions for the future. The panel also talked about the software ecosystem and whether the current one is mature enough to support large-scale HPC deployment on RISC-V. Panellists also offered their views on how the open-source nature of RISC-V would ensure standardization and avoid fragmentation in HPC implementations, ideas on cost and economic viability, energy efficiency and sustainability and IP issues – which relates to Europe’s strive for sovereignty.

The event was followed by EUPEX Forum presentations, which were open to all EPI Forum attendees to listen to free of charge.

All EPI Forum presentations are available in our repository here: https://www.european-processor-initiative.eu/dissemination-material/epi-forum-in-barcelona/, while highlight videos from presentations will be published on EPI YT channel here: https://www.youtube.com/@EuropeanProcessorInitiative.

Next year’s Forum will be held in Paris, stay tuned for more info!

The European Processor Initiative (EPI), a project with 27 partners from 10 European countries, with the goal of helping to achieve EU independence in HPC chip technologies and HPC infrastructure is proud to announce the first EPI Forum to be held in Barcelona, Spain, October 9-10, 2024.

Why attend?

For the first time, the largest project spearheading European efforts to power exascale supercomputers is inviting experts to meet and discuss progress, results and ways ahead for the European exascale processors and accelerators.

Attendees are expected to hear keynotes from industry leaders and champions in the field, keynote on AI by GENCI, keynote on Supercomputing by BSC and a keynote on the HPC future by EuroHPC as well as industry views from Platinum EPI Forum sponsors: Arm, Eviden, NVIDIA, and Gold EPI Forum sponsors: AMD, Semidynamics and SiPearl.

Forum will present an overview of EPI achievements and future plans including Rhea GPP, RISC-V based EPI accelerator cores and various applications. Each day will conclude with a panel discussion with distinguished panellists giving boarder views on presented topics.

EPI invites you to take part in this event, with EPI experts and global technology providers from all over the globe, shaping the future of HPC!

Registration

Registration is open at the EPI website: https://buy.stripe.com/14k3dz0OH9t40us9AA, and all other details regarding the event and policies are available on our website here: https://www.european-processor-initiative.eu/epi-forum-2024/

Venue

EPI Forum will be held in beautiful Barcelona, at the Barceló Sants hotel. The Forum will be organized in two days: the event starts on Oct 9 in the afternoon and continues with morning sessions on Oct 10. In the afternoon of Oct 10, our colleagues from EUPEX project will continue with their event at the same venue, which you can find out more about here: https://eupex.eu/events/eupex-forum-at-the-epi-forum/

We look forward to seeing you at the EPI Forum!

 

The 2024 edition of the ACM Summer School on HPC Architectures for AI and Dedicated Applications, organized by The Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC), will take place in Barcelona from 2-6 September 2024. This year’s program focuses on the convergence between HPC and AI, and it will also explore emerging research areas such as Quantum Computing. The school targets PhD and recent postdocs in HPC and AI. Exceptionally, outstanding MSc students with proven interest and/or experience in projects related to HPC and/or AI are also accepted. Participation in the school is free of charge. Sixty accepted participants will spend one week in Barcelona, attending formal lectures, invited talks, and other activities. The school will cover accommodation expenses and catering during school hours.
More information: https://europe.acm.org/seasonal-schools/hpc/2024

For another year, the entire European and global HPC community gathered to attend the ISC24 in Hamburg, Germany, seeing that it is likely the biggest and most important European HPC conference.

The theme was “Reinventing HPC into ISC 2024” and it was attended by more than 3,400 people in the Exhibition part, with more than 160 exhibitors at their respective booths.

The European Processor Initiative co-hosted a booth together with our colleagues from EUPEX and EUPILOT projects, where our tireless researchers and staff answered numerous questions about the activities in our project.

Colleagues from Barcelona Supercomputing Center, Filippo Mantovani and Fabio Banchelli Garcia, performed an EPAC prototype demo with a RISC-V vector processing unit, which garnered a lot of interest from participants.

On Wednesday, representatives from all three projects co-organized a Birds of Feather session called “European Processor Initiative & the Pre-Exascale Pilots”. The speakers were Pascale Bernier-Bruna (Eviden), Etienne Walter (Eviden), Carlos Puchol (BSC), and the session was moderated by Romana Konjevod (BSC). All three projects presented their goals in a short slide deck, and then opened the floor to a Q/A session. The BoF session had a full house, with many interested ISC attendees coming to participate in the discussion.

Collaboration among European research initiatives is crucial for the optimization of novel technologies and optimization of software. Thanks to the participation of Barcelona Supercomputing Center (BSC) and Polytechnic University of Valencia (UPV) researchers in the European eFlows4HPC and EPI projects, they developed optimised kernels for machine and deep learning (DL) operators that can replace the compute-intensive simulations in application workflows. EPI has provided a set of hardware/software tools for testing EPAC-VEC demonstrating that this technology can significantly accelerate the performance of the convolution.

After three years of research, the European project eFlows4HPC came to its end in February 2024. One of its target architectures was to investigate the benefits of novel computer architectures, such as the ones from EPI. eFlows4HPC experts optimized kernels for specific heterogeneous architectures. In particular, they optimised kernels on ARM-based architectures, equipped with “narrow” SIMD arithmetic units (single instruction, multiple data) arithmetic units, and RISC-V architectures, equipped with long vector processing units such as the one proposed in EPI, putting a strong emphasis on portability.

In addition, BSC and UPV experts migrated some of the computational kernels in the eFlows4HPC workflows to the EPI. eflows4HPC experts tested SVD on EPI hardware obtaining a clear the reduction of execution time from using the VPU (vector version of the routines) compared with an execution only using the RISC-V core (scalar version).

One of the eFlows4HPC Key Exploitable results (KER) is Convolution operators on multicore ARM and RISC-V architectures (CONVLIB), fully developed by UPV. CONVLIB is a library containing high performance implementations of convolution algorithms for multicore platforms with ARM and RISC-V architectures. It contains a driver routine that identifies the best values for four hyper-parameters: micro-kernel, cache configuration parameters, parallelization loop and algorithm, automatically adapting the call to the dimensions of the convolution operator. At EPAC-VEC level, UPV researchers in collaboration with BSC experts migrated ConvLIB to exploit the VPU accelerator in this architecture showing that the EPAC-VEC can significantly accelerate the performance of the convolution. “These experiments show that the EPAC-VEC can significantly accelerate the performance of the convolution, but it does require a very careful implementation of the codes”, states Enrique S. Quintana, UPV professor and eFlows4HPC work package leader. This library is now available at the open software repository here: https://github.com/hpca-uji/ConvLIB

The results of this research have also been published in the following peer-reviews publication:

Ramírez, A., Castelló, and E. S. Quintana-Ortí, “A BLIS-like matrix multiplication for machine learning in the RISC-V ISA-based GAP8 processor,” J. of Supercomputing, 2022. https://doi.org/10.1007/s11227-022-04581-6.

About eFlows4HPC

eFlows4HPC is a European-funded project with a budget of €7.6M that started on 1 January 2021 and lasted 3 years and 2 months. Coordinated by BSC (Spain), the project brings together a multidisciplinary consortium: CIMNE (Spain), FZJ (Germany), UPV (Spain), ATOS (France), DtoK Lab (Italy), CMCC (Italy), INRIA (France), SISSA (Italy), PSNC (Poland), UMA (Spain), AWI (Germany), INGV (Italy), ETHZ (Switzerland), Siemens (Germany), and NGI (Norway).

The eFlows4HPC project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 955558. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Germany, France, Italy, Poland, Switzerland, Norway. It also received funding from MCIN/AEI/10.13039/501100011033 and the European Union NextGenerationEU/PRTR (PCI2021-121957).

Copyright 2022 All Right Resereved

This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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