ESiWACE2 Virtual Workshop on Emerging Technologies for Weather and Climate Modelling was held online last week, by the Centre of Excellence in Simulation of Weather. Two of EPI’s distinguished experts participated with topics related to EPI and HPC – Jean-Marc Denis, from Atos, and Jesus Labarta, from BSC.

Jean-Marc Denis’ presentation was focused on the changes in the HPC field lately, the death of Moore’s law and the inevitable changes and challenges it brings to the future. He also gave an overview of EPI’s approach to the development of a European chip and our roadmap, with respect to those changes. Jesus Labarta, in a presentation titled Future HPC systems made in Europe, presented the vision and status of the EPAC development and offered the possibility to attendants to try their codes/mini apps in our co-design studies on the RISC-V vector emulator.

The materials are published in our repository:


The European Processor Initiative (EPI) is building a new central processing unit (CPU) with European technology. This CPU will bundle an accelerator, based on the open source RISC-V architecture. This accelerator will include support for the upcoming V-extension of RISC-V. At the Barcelona Supercomputing Center (BSC), we have been busy at work building software tools and infrastructure to explore and learn about the benefits and challenges that this extension brings to the table.


RISC-V is a relative newcomer in the Instruction Set Architecture (ISA) space, along with well-established ones like x86-64 and AArch64. Its main distinctive feature is that it is an open source specification that anyone can take to implement and extend, be it for commercial purposes or research studies. The specification is maintained by the RISC-V Foundation and its members.

Another important aspect of the RISC-V ISA is the fact that it has been designed to be modular. Conscious that not all the features present in modern ISAs may be of interest to everyone, the ISA is structured in a base specification and a set of standard extensions. Also, given its open source nature, anyone can define their own non-standard extensions, and the ISA caters to that possibility by providing customization features. Standard extensions have the advantage that they are eventually ratified by the RISC-V Foundation and its members after a collaborative development of the specification and gathering of experience in early implementations.

The V-extension

Standard extensions are commonly identified with a single letter. One of them is the V-extension. V stands for vector. This extension aims to provide vector computation capabilities to the RISC-V ecosystem. It is currently under development so no hardware or software exists that supports it.

Programs running on a computer are made up by a number of instructions. Each instruction is executed by the CPU, and most of them just do a simple operation on a single data value. For instance, an instruction may add two numbers. While this is perfectly reasonable for most applications, there are several domains, spanning from High Performance Computing (HPC) to Digital Signal Processing (DSP), where applications need to repeatedly perform the same computation over a regular set of data. In our running example, rather than just adding two numbers, applications in these domains are better served by an instruction that is able to add, pair-wise, two sets of numbers. These sets of numbers are called vectors (conversely, a single number is called a scalar). In this scenario, using vector instructions can result in applications that run more efficiently both in time and in energy consumption.

These kind of instructions traditionally have been called Single Instruction Multiple Data (SIMD), as a single instruction is able to operate over a set of data instead of individual elements. Many of the well-established vendors like Intel and Arm already provide SIMD instructions in the ISAs they maintain. Examples are Intel’s SSE, AVX-2 and AVX-512 and Arm’s Advanced SIMD and SVE.

There are a number of distinctive features in the V-extension that make it very interesting and also pose some challenges to implementers. An important one is that the extension does not prescribe the length of the vectors. Traditional SIMD ISAs prescribe the size of a vector as 128, 256 or 512 bit. A drawback with this approach is that a new ISA is required every time there is an interest to enlarge the vectors. The alternative is to allow the vendor to choose the size depending on its market needs. For instance, this is what Arm’s SVE does, where vectors can range from 128 bit to 2048 bit, in multiples of 128 bit. The V-extension currently only requires the width to be a power-of-2, so it is possible to cover markets that are well served with shorter vectors, like DSP, and also markets that benefit from longer vectors, like HPC.

Another interesting feature of the V-extension is that it restores the concept of vector length, a feature reminiscent of ancient vector architectures of the 1970s. The vector length tells the CPU how many elements in the vector have to be processed.

SIMD ISAs often process the whole vector so this concept does not exist there. An application has to consider the case when there is not enough data to fill a full vector. One option is to resort in this case to regular, scalar, instructions. Another option is to keep using vector instructions but discard some of the results computed, using a common feature called masking that may come with an extra penalty. The vector length can be used to reduce the number of elements being processed without requiring extra instructions, like in the first option, or having to compute a mask. For some implementations like in EPI’s VPU, shortening the vector length also allows to shorten the latency of instructions – no computation cycle is needed for the unused “tail” of the vector.


To explore the software side of the V-extension, we took the LLVM open source compiler which, except for the V-extension, already has good support for a number of the standard extensions of RISC-V. LLVM is an umbrella project for open source compiler and other toolchain-related projects like linkers or static analyzers.

In order to enable the exploration of the V-extension, we designed and implemented an initial set of C/C++ builtins. These builtins allow the C/C++ developers to be able to target the V-extension instructions from their applications. Along with our partners at EPI, we have ported several computational kernels, core parts of applications that are used very frequently, using the developed builtins. Some of those kernels are classic in HPC, such as matrix multiply, sparse matrix vector and the FFTW implementation of the Fast Fourier Transform (FFT). Algorithms from other domains, such as cryptography, have also been evaluated under the V-extension.

Finally, we also implemented in the compiler initial autovectorization support. A compiler can determine that vector instructions can be used without having to use builtins. Because of the two distinctive features of V-ext described earlier, compilers do not have good support yet in this area. Most of our work here is very infrastructural in making sure the compiler can vectorize in the way we believe is the best for the V-extension. We hope to be able to provide better support in this area, which is under intense work-in-progress status.

The V-extension is still being built, so no hardware exists that can execute V-extension instructions. This limits users and developers of the compiler as they would not be able to tell if their program and the compiler work correctly. To unblock this issue, we developed an emulator, called Vehave, that runs on top of existing RISC-V Linux platforms. This way the correctness of the applications and the compiler can be validated using the emulator.

We also implemented in the emulator a mechanism to generate traces of the executed vector instructions. These traces can be loaded in BSC’s trace visualization tool Paraver. This provides information valuable to the users and developer of the compiler.

For instance, application developers can determine that their application requires the compiler instructions that are known to be slow in a specific implementation of the V-extension. Compiler developers can identify redundant instructions or complicated instruction sequences. At BSC, we identified some of those complicated instruction sequences and we reported to the V-extension work group. The specification was extended with new individual instructions that achieve the same functionality of the original sequences.

In order to allow quicker experimentation, since all compilers are large pieces of software, we installed a version of Compiler Explorer that can work with the compiler we developed. This way it is possible to share small snippets of code to evaluate the quality of the code emitted by the compiler. This tool is publicly available at

The Initiative will gather experts to discuss exascale future on March 16-17, in Paris

The European Processor Initiative is announcing the first EPI Forum to take place in Paris, France, on March 16-17, 2020.

EPI is going full speed ahead to meet the goals of our mission – European independence in HPC technologies and a favorable global position in the race towards exascale.

In a two-day event, the consortium will host experts from HPC ecosystem, engineers, researchers and global players in the field, to attend sessions, round tables and keynote speeches from prominent executives and experts.

Hosted near the beautiful Champs-Élysées, at the Elysées Biarritz venue, the first day of the event will tackle interesting topics such as architecture choice, the rise of EPI Common Platform as an EU central computing unit, an overview of processing cores, and the introduction of SiPearl, EPI’s industrial hand.

The forum will also provide the attendees with inputs and worldwide views from technology providers and intriguing discussion regarding bringing new EU HPC processor to market and associated challenges. Prominent keynotes include experts such as Brent Gorda, senior director of HPC, Infrastructure Line of Business Arm, Steve Scott, SVP, Senior Fellow & CTO of the HPC & AI Business Unit at HPE, Paul de Bot, Senior Director, TSMC Europe B.V., Mitsuhisa Sato, Deputy Director, RIKEN Center for Computational Science, and Robert Hoekstra, PhD, Manager, Scalable Architectures, Computing Research Center, Sandia National Laboratories.

The second day of the EPI Forum will feature a keynote speech from RISC-V Foundation CEO, Calista Redmond, followed by discussions on automotive and edge HPC, EPI software stack, programming models, use of accelerator cores and exascale applications.

“EPI project is strongly supported by the European Commission and we are proud to serve the European ambition toward sovereignty. As sovereignty is becoming more and more important, EPI is going to play a central role in the European HPC landscape. Initially, with the design of the RHEA processor, on next-generation Arm® Neoverse™ architecture, we are going to equip the European exascale supercomputer. In parallel, as part of our long-term strategy, we are starting to build foundations for our future European IP toolbox based on a variety of IP solutions including RISC-V, which will target custom accelerators and microprocessors.  Our ambitious vision should begin to show concrete results with first-generation processors by SiPearl in the field by 2022. The first EPI Forum, much like the project itself with its strategy of supplying products in the short term and achieving EU sovereignty in the long term, will allow attendees to become acquainted with how those short- and long-term ambitions are tightly articulated,” stated Jean-Marc Denis, EPI Chairman of the Board.

“There is demand for the type of performance and innovation that Arm Neoverse-based processors deliver, and this is evident in the growth of the Arm HPC ecosystem,” said Chris Bergey, SVP and GM, Infrastructure Line of Business, Arm.  “Our collaboration with the EPI and SiPearl is strategically important to our goals in HPC, and Arm supports the EU on its road toward greater processor independence and exascale deployments.”

“As the European number one in High-Performance Computing, Atos is fully supportive of the EuroHPC Joint Undertaking’s ambitious strategy to boost European technological self-reliance. Atos is proud to lead the effort to design a family of European processors for HPC and for other emerging markets, in our role of coordinator of the EPI project. Atos has a long history of commitment to the development of the Arm ecosystem for HPC, particularly through our role in the pioneering Mont-Blanc projects. With EPI, we are taking this ambition to a different scale, and this is good news for the robustness of the European industry,” said Arnaud Bertrand, Senior Vice President, Global Head of BDS Strategy, Innovation and R&D at Atos.

“HPE has been a strong supporter of the Arm ecosystem with both our Apollo and Cray systems and software for HPC and AI and we are excited to partner with SiPearl and the EPI consortium,” said Peter Ungaro, senior vice president and general manager, High-Performance Computing and Mission Critical Solutions, HPE. “As the leader of the global hybrid IT and HPC markets, HPE is uniquely positioned to leverage and distribute SiPearl processors on future systems to customers around the world.”

“The future of computing is dramatically changing, driven by the digitalization of many industries as compute workloads change with the arrival of big data,” said Ravi Subramanian, senior vice-president at Mentor, a Siemens Business. “The European Processor Initiative is the most significant pan-European initiative in computing over the past two decades. Mentor is excited to participate in and contribute to this initiative by bringing key experts together in Paris for the first EPI Forum to help chart the future of the entire EPI ecosystem.”

“As a key partner to the European Processor Initiative, we are proud that our solutions contribute toward the creation of state-of-the-art high-performance computing processor technologies designed in Europe, “ said Luc Elman, VP Customer Excellence Europe at Synopsys.”

“GENCI as a French actor of the HPC-driven and AI-driven simulation activities in science is very proud to participate and support the EPI initiative which will achieve a major contribution to the European sovereign digital revolution supported by co-designed exascale systems funded by EuroHPC,” said Philippe Lavocat, President and CEO of GENCI.

Event details and registration is available at



The 20th HiPEAC conference held in Bologna, Italy, from January 20th to 22nd is behind us and it was a special event for the members of the Initiative. In addition to being a sponsor of the conference, with a booth visited by many attendees, EPI members made themselves a busy schedule, participating in sessions on each day of the conference.

On the first day, Imen Baili from Menta, participated in the WRC: Workshop on Reconfigurable Computing, with a presentation titled European Processor and the role of eFPGA, where she spoke about FPGA applications and the difference between Menta’s eFPGA solution VS FPGA. She also addressed the advantages such a solution brings to EPI, offering the most robust verification flow as well as the fact that pure digital IP guarantees very fast delivery.

On the second day of the conference, John Davis, from BSC attended the Eurolab4HPC Industrial Session on Open Source Hardware and introduced LOCA – the European Laboratory for Open Computer Architecture. In his presentation, he also addressed the RISC-V involvement in EPI.

In addition to the sessions and EPI workshops organized, Fabrizio Magugliani from E4 and Andrea Bartolini from the University of Bologna, held a 10-minute industry session introducing EPI and inviting the attendees to attend the EPI Tutorial.

On the very last day, after discussing with many interested attendees and STEM students, EPI team organized our own tutorial titled “First steps towards a made-in-Europe high-performance microprocessor”, covering the latest in EPI.

Josip Knezović, from UNIZG-FER, gave a general introduction into the tutorial, while Denis Dutoit from CEA covered General EPI overview and details of EPI’s Common Platform and Rhea 1st implementation.

Mauro Olivieri from BSC and Andrea Bartolini from UNIBO followed up with two very important aspects as well – accelerators in EPI and EPI power management, while the first section of the tutorial was closed by a presentation from Fabrizio Magugliani from E4 on EPI PCIe daughter card as a software development vehicle. After a short break, BSC’s team members Filippo Mantovani and Roger Ferrer Ibáñez closed the tutorial with a session on Bringing up EPI RISC-V Vector architecture Software, with a demonstration on software-emulated vector instruction explorations for RISC-V-based accelerator.

Materials and presentations from EPI’s sessions are available in our Dissemination repository:

SiPearl, EPI’s industrial and business hand, joins the EPI consortium as its 27th partner and moves into its operational phase.

SiPearl and its solutions will help drive the development of the European market for high-performance computing (HPC), as well as its strategic applications such as artificial
intelligence and connected mobility. SiPearl will develop and market its solutions through close collaboration with its 26 partners from the EPI – scientific community, supercomputing centers and leading names from the IT, electronics and automotive sectors – which are its stakeholders and future clients.

Read the full press release here:  and visit the company website here:

The project is finishing its first year with introduction of a new EPI Common Platform, an updated roadmap and presence at key events

The European Processor Initiative (EPI), a project with 27 partners from 10 European countries, with the goal of helping the EU achieve independence in HPC technologies, is approaching the closure of the first year in its three-year cycle.

During that time, the consortium has submitted several architectural designs to the European Commission and is now ready to show its updated roadmap to the public.


Figure 1. EPI Roadmap

The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.

The Rhea chips will be integrated into test platforms, both in workstations and supercomputers in order to validate the hardware units, develop the necessary software interfaces, and run applications. Rhea aims to be the European processor for several experimental platforms towards exascale HPC and future automotive designs.

Today we also announce our long-term commitment to our recently introduced initiative to harmonize the heterogeneous computing environment by defining a common approach: the EPI Common Platform (CP). The EPI CP is in early development but will include the global architecture specification (hardware and software), common design methodology, and global approach for power management and security, in the future.

The CP in the Rhea family of processors will be organized around a 2D-mesh Network-on-Chip (NoC) connecting computing tiles based on general purpose Arm cores with previously mentioned accelerator tiles.

Figure 2. EPI Common Platform

A common software environment between heterogeneous computing tiles will harmonize the system, acting as a common backbone of IP components for IO connection with the external environment such as memories and interconnected or loosely coupled accelerators.

With this CP approach, EPI will provide an environment that can seamlessly integrate any computing tile. The right balance of computing resources matching the application needs will be defined through the carefully designed ratio of the accelerator and general-purpose tiles.

These important developments and more will all be presented at high-profile events the Initiative is attending, announced on EPI’s web:

We invite all interested parties to visit our exhibition booths at upcoming events, with special focus on the Supercomputing Conference in Denver, USA (Nov 17-22, 2019), booth #895, and the European Forum for Electronic Components and Systems in Helsinki, Finland (Nov 19-21, 2019).

Meet us there to discuss EPI’s future!

October started pretty busy for EPI partners, who attended various events presenting the latest from the Initiative.

The calendar was launched by members of Atos and CEA attending the RISC-V Week in Paris, which encompassed two major groups: The 2nd RISC-V Meetings, organized by IRT Nanoelec and CEA and The Scientific Day of IRT SE & GDR SOC2: RISC-V for critical embedded systems, organized by IRT St-Exupéry and GDR SOC2.

Romain Dolbeau from Atos gave a talk titled “European Processor Initiative: challenges & opportunities for RISC-V accelerators in an HPC platform”. He described the currently anticipated architecture of the EPI design and how to leverage this architecture in the software, using open standards. In particular, he touched upon how the EPI project is developing IP for a set of RISC-V-based accelerators designed to connect directly to the processor network-on-chip. He also discussed EPI plans to integrate those IPs in a silicon device, and how other accelerators IP designers could leverage EPI to create new high-performance multi-chip processing devices.

At that same event, Denis Dutoit from CEA gave a talk titled “European Processor Initiative: First step towards a made-in-Europe high-performance microprocessor”. After an introduction on High Performance Computing new challenges and associated technology/architecture evolution, the presentation highlighted the EPI position statement on generic computing, accelerator with RISC-V and design methodology. The presentation concluded with an explanation of EPI’s roadmap towards a wide range of applications from Exascale computing to embedded HPC.

Italian partners also had a very busy week presenting EPI in several workshops and distinguished lectures. Fabrizio Magugliani from E4 Computer Engineering presented at the workshop “Edge computing: Quando il Cloud è troppo lontano”, which confirmed the need for integrating the different streams of data (coming from IoT, the Edge, Industry 4.0 and similar sources) in a consistent view, including the pre-processing of data at the Edge and a HPC-powered analysis in a centralized facility, applying AI and HPDA techniques to the streams and then storing and capitalizing on the ‘knowledge’ extracted from the data. He introduced the roadmap and goals of the EPI and highlighted that the roadmap is fully consistent with the computational need of such a chain of processing.

Only two days later, he also presented at the 12th International Conference on Internet and Distributed Computing Systems in Naples. The speakers listed in the rich agenda detailed how the rapidly evolving technology for Distributed Computing Systems enables to use more computation and ‘intelligence’ at the Edge, and how to maximize the effectiveness of different architectures and components. While these components are ideal for analyzing data at the Edge, more elaborate analysis demands the use of more powerful systems. Having the same Instruction set at the Edge (running Arm devices) as well as in the centralized computing facility is definitely a value, making the EPI processor ideal for seamless integration of the data streams with the EPI-powered centralized facility.

Coming from EPI’s academic wing, University of Pisa’s Prof. Sergio Saponara was invited to give a lecture at the IEEE I&M France Chapter/GDR SoC2 Workshop. He held an IEEE IMS DL about ACES (autonomous, connected, electrified and shared) vehicles and related instruments and measurement/perception tools. The IEEE DL presented the opportunities and challenges of the ACES trends, with a focus on high-performance machine-perception sensors (like Radar, Lidar, Camera), navigation and positioning technologies (Inertial Measurement Units, Global Position/Navigation Satellite Systems). The challenge of the High-Performance Computing, needed on-board the vehicles to process in real-time such large amount of data, using either deterministic signal and data processing techniques or new machine learning and AI tools, have been also discussed. To this aim, the opportunities offered by EPI have been also presented.

Addressing the HPC user community, EPI Chair of the Board, Jean-Marc Denis, attended two HPC User Forums this week – the first in Lugano, Switzerland, and the second in Edinburgh, Scotland, where he presented the road so far, the latest developments and the Initiative future steps.

Across the ocean, another EPI industrial partner, Menta, attended the Arm TechCon in San Jose, California with their exhibition space at which they offered EPI materials for the interested attendees.

The automotive segment of EPI also had a busy week. Karlsruhe Institute of Technology held the first automotive summit in cooperation with the Tongji University in Shanghai. Many representatives from research and companies in China such as BMW, Infineon, Intron and UAES (Bosch in China) participated and gave interesting presentations about their current and future R&D projects. One major topic was autonomous driving and how it can be accomplished with the currently available computing resources, also with solutions ranging from edge and cloud computing to embedded HPC. This discussion naturally included KIT’s participation in EPI, which is why Prof. Jürgen Becker gave an interesting talk about the recent research activities in Germany and Europe also mentioning the on-goings in EPI and the known partners in the consortium. The project and plans were well received by the audience.

October schedule is still not finished, with several more events to go, all of which are announced at EPI’s web calendar:, serving as a perfect ramp-up to Initiative’s attendance at Supercomputing in Denver, US and EFECS conference in Helsinki, Finland in November. Meet us there!



Last week has been loaded with activities for the European Processor Initiative. Our team attended several very important events, where EPI was discussed and our road to the low-power processor presented.

EPI Chairman of the Board, Jean-Marc Denis, attended two events, in a Transatlantic hop, skip and a jump: first, the 73rd HPC User Forum in Chicago, where he presented EPI’s objectives and its interlink with the European Union’s EuroHPC Joint Undertaking, only to go back to Parallel Computing conference in Prague, with a similar mission. His talk concluded in presenting EPI’s challenges for the upcoming period: building on existing IP and communities and closing the gap between research and innovation and industrial products.

At the same time, beautiful cities of Bologna and Pisa hosted two events where the Initiative presented its objectives and roadmap.

In Bologna, at the Italian Workshop on Parallel and High-Performance Computing Technologies, the European Processor Initiative presented the EPI project to the Italian HPC academia and to the industrial users.

The academic participants presented their research lines and their previous engagement and contributions to EU programs, covering a wide spectrum of research fields and technological implementation. Andrea Bartolini (UniBO) presented the goals of the EPI, the members of the consortium and the roadmap for the processor, the accelerator and the automotive components, and highlighted the role of University of Bologna in the development of key components of the EPI project. Fabrizio Magugliani (E4 computer Engineering) presented the role of E4 in the development of key components of the EPI projects such as the PCIe daughter board hosting the EPI processor as Software Development Vehicle. The presentation opened a healthy discussion about how the community of Italian researchers could leverage the EPI project bringing the results of their research and therefore adding value to the project.

In Pisa, the EPI team participated at the RoundTable at ApplePies, 7th International Workshop Applications in Electronics Pervading Industry, Environment & Society. The Round Table confirmed that the EuroHPC Joint Undertaking, in full alignment with the objective of deploying in Europe a world-class supercomputing infrastructure and a competitive innovation ecosystem in supercomputing technologies, applications and skills by coordinating the efforts of its member states and share resources, has assigned one of the 3 Precursor to Exascale system to CINECA. Building on that, the Round Table’s participants presented the contribution of Italian-based institutions and enterprises towards the maximization of the results achieved through exascale-class systems both from the scientific and research point of view as well as from the industrial point of view. The current status of R&D in Italy specifically for the development of components for exascale-class systems was addressed, including the role of Italian institutions and enterprises in the European Processor Initiative (EPI) consortium, and which synergies among the key players could create a native Italian ecosystem fully aligned within the EuroHPC JU and EPI initiatives for enabling exascale-class systems to support scientific leadership and industrial competitiveness.

The week was finished by Atos team members participating at the Arm Research Summit in Texas, USA. Romain Dolbeau and Ying-Chih Yang gave a talk at the workshop “Impact of Arm hardware from an HPC application perspective (present and future-looking)”. The key objective of the workshop was gathering expertise from various research groups (runtime systems, linear algebra, operating system, performance modeling,…) to discuss key features and shape next-generation applications.

Partners from the European Processor Initiative organized and held their first public tutorial on EPI called “First steps towards a made-in-Europe high-performance microprocessor”. It was held on July 17th, at the Universita Politècnica de Catalunya, co-located with the ACM 2019 Summer school on HPC architectures for AI and dedicated applications.

EPI distinguished experts presented in front of a young and highly motivated audience, with more than 40 attendees in the audience. After a welcoming address by Fabrizio Gagliardi from BSC, presenters Andrea Bartolini (UNIBO), Mauro Olivieri (BSC), Jesús Labarta (BSC), Jaume Abella (BSC) and Francisco Cazorla (BSC) talked about the HPC landscape and the Initiative through several lectures.

The tutorial highlighted the challenges, trends on the processor’s technology in the High-performance computing market, and the opportunities for European technologies to play an active and leading role in the Exascale race.

The presenters explained why it was the right moment for a European computing platform and how EPI would address the challenge of creating an HPC platform which addresses the computing needs for future homogeneous and heterogeneous large-scale and autonomous driving automotive systems.

Presenter Andrea Bartolini, UNIBO, said after the tutorial: “It has been a pleasure to serve as the first presenter at the first EPI tutorial, co-organized at the ACM 2019 Summer school on HPC architectures for AI and dedicated applications on-going now in the beautiful Barcelona city. A new wave of young researchers and graduated students now know the challenges and opportunities which Europe is facing with EPI towards a made-in-Europe high-performance microprocessor.”

Presentations from the tutorial are available under the Dissemination and communication repository on EPI web, while the video materials of the tutorial are available at the EPI YouTube channel.

NVIDIA announced its support for Arm CPUs, by making available to the Arm® ecosystem its full stack of AI and HPC software — which accelerates more than 600 HPC applications and all AI frameworks – by year’s end.

The stack includes all NVIDIA CUDA-X AI™ and HPC libraries, GPU-accelerated AI frameworks and software development tools such as PGI compilers with OpenACC support and profilers.

Once stack optimization is complete, NVIDIA will accelerate all major CPU architectures, including x86, POWER and Arm.

Philippe Notton, general manager of EPI, said that the European Processor Initiative aims to endow the European Union with its own high-end, low-power, general purpose and accelerator solutions. EPI and SiPearl, its industrial hand, consider very positively the new possibilities offered by NVIDIA. The combination between the EPI Arm-based microprocessor and NVIDIA accelerator could make a perfect match for equipping building blocks in the future European exascale modular supercomputers.

The full article is available at nvidianews.

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