EuroHPC Summit 24, a conference gathering European key stakeholders and users in the high-performance computing field, was held from March 18 to March 21, 2024, in Antwerp, Belgium.

The conference gathered more attendees than ever before, who were eager to see that is new in the European HPC space and perhaps eager to visit poster sessions, demos or finally, get a special look into the work of European supercomputers.

The European Processor Initiative was present at the event. Our CCO, Mario Kovač, attended the poster sessions explaining how far along we are in the project timeline.

Colleagues from Barcelona Supercomputing Centre showcased the EPAC chip, the first RISC-V based prototype leveraging vector acceleration coming from the EPI project.

EPI’s General Manager, Etienne Walter, and SiPearl’s CEO and founder, Philippe Notton, attended the parallel sessions on European Chip Initiatives for HPC, where they gave a detailed overview of what EPI is doing right now and what kind of developments can be underway for Rhea1 and Rhea2 processors.

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 30 partners from 10 European countries, with the goal of achieving Europe’s independence in HPC chip technologies and infrastructure, is proud to announce the successful Manufacturing and Silicon Demonstration of its EPAC Accelerator chip version 1.5, marking a significant milestone in high-performance computing.

EPAC1.5 is a collection of RISC-V based accelerators designed to push the boundaries of acceleration technologies. This innovative test-chip showcases three distinct approaches to acceleration:

1. General purpose CPU with dedicated vector unit (VPU)
2. Many-core stencil/machine learning accelerator (STX)
3. General Purpose CPU supporting variable precision (VRP)

The EPAC 1.5 design (Figure 1) contains vector processing micro-tiles (VPU) composed of the Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb.

Additional micro-tiles contain distributed Home Nodes (HN) and L2 cache slices (L2), designed respectively by Chalmers and FORTH-ICS, that provide a coherent view of the shared memory subsystem.

The chip also includes the Stencil and Tensor accelerator (STX) designed by ETH Zürich and Fraunhofer IIS and the variable precision processor (VRP) designed by CEA.

All accelerators are interconnected with a very high-speed network on chip with multiple crosspoints (XP) and an off-chip link using SERDES technology from EXTOLL.

Figure 1: EPAC 1.5 chip floorplan illustrating the major blocks

The physical design was performed by Fraunhofer IIS using GLOBALFOUNDRIES 22FDX low-power technology. The chip is 27mm² with 0.3 billion transistors and is hosted on a daughtercard designed by E4 (Figure 2).

The complex bring-up and Linux boot process was carried out at FORTH-ICS, Heraklion, Crete, Greece, and EXTOLL, Mannheim, Germany.

Figure 2: EPAC 1.5 chip on daughtercard

The EPI team demonstrated Linux boot (Ubuntu 22.04 LTS) in both command-line and graphical user interface modes (Figure 3). This demonstration seamlessly integrated the execution of High-Performance Computing (HPC) kernels, harnessing the impressive power of the vector processing unit within the vector accelerator.

Figure 3: EPAC 1.5 running Ubuntu 22.04 with GUI

“Seeing a standard Linux distribution’s GUI boot on a chip developed through collaborative efforts within the European Union consortium has been nothing short of thrilling,” declared Filippo Mantovani, the coordinator of the EPAC effort at BSC.

Roger Espasa, founder and CEO of Semidynamics, shared his enthusiasm, stating, “The Avispado core by Semidynamics is an integral part of EPAC, and we take immense pride in our role within this successful EU endeavor. Semidynamics’ development of Avispado has been advanced by EPI funding, propelling the EPAC architecture forward over the past four years.”

Vassilis Papaefstathiou, Head of the bring-up team at FORTH-ICS, added: “It has been an incredible journey for our team from the very early stages of EPAC 1.5 bring-up to booting Linux and running demanding benchmarks. We are extremely proud to be part of the EPI team and contribute to this success.”

The successful bring-up of EPAC 1.5 is a major step in the development of the EPI common platform, showcasing the variety of accelerators that can be integrated in future European supercomputers to efficiently address a wide range of compute problems.

For more comprehensive details about EPAC, please visit EPI website http://www.european-processor-initiative.eu/accelerator/.

About EPI

The European Processor Initiative (EPI) is a project whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

The project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 30 partners from 10 European countries, aiming to make the EU independent in HPC chip technologies and HPC infrastructures, is proud to announce that it has delivered a significant European sovereignty contribution with valuable business impacts.

One of its key partners, Eviden, the Atos Group business leading in advanced computing, as part of a consortium together with ParTec, the German modular supercomputing company, have won an emblematic contract with EuroHPC to provide the very first Exascale supercomputer in Europe, named JUPITER. SiPearl, another key EPI partner, will provide its brand new Rhea1 processor, an outcome of the EPI initiative [1], the first HPC-dedicated European processor on the market with exceptionally high memory bandwidth. JUPITER is a EuroHPC JU supercomputing infrastructure that will be operated by Forschungszentrum Jülich in Germany. This is a major milestone for SiPearl and EPI in fulfilling the European Union’s mission to ensure European sovereignty through the return of high-performance, low-power processor technologies in Europe. It will contribute to the development of high-precision models of complex systems and artificial intelligence applications to solve strategic, scientific, industrial and environmental challenges with a low-carbon footprint.

JUPITER will be composed of two partitions, a highly scalable GPU accelerated Booster Module and a general-purpose Cluster Module with high memory bandwidth processors. The general-purpose Cluster Module will be based on SiPearl’s first-generation processor, Rhea1. Using the Arm® Neoverse^TM V1 platform, the Rhea1 is characterized by very high memory bandwidth, extraordinary compute performance and efficiency for an unmatched Byte/Flop ratio. It will help JUPITER run complex simulations and artificial intelligence applications to solve strategic, scientific, industrial and environmental challenges with a low-carbon footprint. Rhea1 will be available in 2024.

“I am proud of this outstanding achievement, and I value the EPI team’s cooperation. Together we are paving the way towards Europe’s technological sovereignty. This is creating an unprecedented momentum for EPI to deliver its promises: European processors and accelerators for European exascale supercomputers. EPI is committed to supporting Eviden, Jülich, and SiPearl, key members of EPI, as well as Partec that is close to us, to make JUPITER a great European success” – said Eric Monchalin, Chairman of the EPI Board.

“JUPITER’s dynamic modular architecture will demonstrate the benefits of using different processor types such as CPUs and GPUs in dedicated compute modules. We are excited about the power saving and execution speed opportunities that SiPearl’s unique Rhea processor with its high memory bandwidth, a brainchild of EPI, will open up for JUPITER” – highlighted Prof. Thomas Lippert, Director of the JSC, Forschungszentrum Jülich.

“SiPearl is pleased to take part in this very first European exascale supercomputer. This is a great achievement for us and we look forward to working hand-in-hand with Jülich, Eviden and ParTec, our partners from the EuroHPC ecosystem. The dream of a European machine crossing the exaflop threshold with a European processor inside is coming true”, concluded Philippe Notton, CEO and founder of SiPearl.

“We are extremely proud to be providing our BullSequana XH3000 for the first Exascale supercomputer in Europe and to be supporting our economic and industrial sovereignty. This powerful system will enable new breakthroughs in key sectors, such as medicine and climate change, and stimulate innovation for the whole European scientific community.” said Emmanuel Le Roux, Group SVP, Global Head of HPC, AI & Quantum at Eviden, Atos Group.

“Developing a strong European HPC supply chain with energy-efficient components and technologies is key to achieving digital sovereignty in Europe while promoting more sustainable supercomputing. The fact that a European microprocessor will underpin the first European supercomputer to exceed the one exaflop threshold is a pivotal victory for Europe!” said Anders Dam Jensen, Executive Director of the EuroHPC Joint Undertaking.

About EPI

The European Processor Initiative (EPI) is a project whose aim is to design and implement a roadmap for a new family of European low-power processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

The project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, the Netherlands, Portugal, Spain, Sweden, and Switzerland.

[1] https://eurohpc-ju.europa.eu/procurement-contract-jupiter-first-european-exascale-supercomputer-signed-2023-10-03_en

The European High Performance Computing Joint Undertaking (EuroHPC JU) has launched 3 new research and innovation projects. The projects aim to bring the EU and its partners in the EuroHPC JU closer to developing independent microprocessor and HPC technology and advance a sovereign European HPC ecosystem. The European Processor Initiative (EPI SGA2), The European PILOT and the European Pilot for Exascale (EUPEX) are interlinked projects and an important milestone towards a more autonomous European supply chain for digital technologies and specifically HPC.

With joint investments of €140 million from the European Union (EU) and the EuroHPC JU Participating States, the three projects will carry out research and innovation activities to contribute to the overarching goal of securing European autonomy and sovereignty in HPC components and technologies, especially in anticipation of the European exascale supercomputers.

The three projects have been selected following two calls for proposals: H2020-JTI-EuroHPC-2020-01 for EUPEX and The European PILOT, and H2020-JTI-EuroHPC-2020-02 for EPI SGA2.

Anders Dam Jensen, the European High Performance Computing Joint Undertaking (EuroHPC JU) Executive Director, said:

“Developing a strong European HPC supply chain with independent components and technologies is key to achieve strategic autonomy and digital sovereignty in Europe. The three projects, EPI 2, EUPEX and The European PILOT are critical to make successful our transition towards exascale while developing a world-class, competitive and innovative supercomputing ecosystem across Europe.”

“The EPI consortium brings together the best industrial and academic expertise in Europe: it combines the best of both worlds, academic innovation with industrial strength. We are thrilled to be given the opportunity to build on the momentum generated by phase 1 of the project and continue to develop the technologies that will power future European exascale systems. We look forward to seeing our components (processors & accelerators) experimented and used – in pilot projects and beyond.” said Etienne Walter, Atos, the EPI Phase 2 General Manager.

“All members of the EUPEX consortium are extremely proud to participate in this pilot for exascale, a project on an unprecedented scale, which is the culmination of more than 10 years of European HPC research and development towards exascale supercomputing. EUPEX will crystallize the research efforts of many projects – from Mont-Blanc projects to DEEP projects – and validate EPI processors with all these European technologies within the framework of a coherent but modular pilot platform. EUPEX will pave the way for a self-reliant European HPC industry, capable of delivering exascale-class supercomputers manufactured in Europe.” said Jean-Robert Bacou, Atos, the EUPEX coordinator.

“The European Pilot project will contribute to a sustainable exascale HPC in Europe and it will help build the groundwork for long-term technical independence. Hardware wise, The European Pilot leverages and significantly scales up EPI advancements built from scratch, such as EPAC, in the form of massively parallel arrangement of HPC vector and machine learning accelerators. These European-IP accelerators and customized software ecosystem will deliver near-exascale levels of performance at unparalleled levels of scale of integration. The European Pilot systems will be deployed in liquid immersion cooling tanks supporting ultra-efficient power densities. The know-how to build these supercomputers will help establish digital autonomy within the EU” said Carlos Puchol, Barcelona Supercomputing Center (BSC), the European Pilot coordinator.

European Processor Initiative (EPI)  

The consortium of the European Processor Initiative (EPI) started the second implementation phase of the initiative on 1 January 2022. The project is implemented under the framework partnership agreement in European low-power microprocessor technologies which focuses on microprocessor technologies to develop competitive European technology for HPC and other applications.

Central goals of the initiative are:

• Strengthening the competitiveness and leadership of European industry and science;
• Developing European microprocessor technology with drastically better performance and power ratios;
• Tackling important segments of broader and/or emerging HPC and Big-Data markets.

The second implementation phase of the EPI will continue the initial developments of the phase 1 on a European microprocessor and accelerator to support European technological autonomy and sovereignty in this critical area. Based on a solid, long-term economic approach, the EPI will deliver central components of future European supercomputers to boost innovation and the digital transformation of the European economy.

The specific focus of the second phase is to finalise the development of the first generation of low-power microprocessor units and accelerators, enhancing existing technologies to target the incoming European Exascale machines, develop the second generation of and ensuring paths for industrialisation and commercialisation of these technologies.

The microprocessors units are leveraging on Arm architecture, and the accelerators on Risc-V instruction set architecture. The EPI has established close links to two pilots towards the European exascale supercomputers where the developed technology will be demonstrated and made available for software development.

The project is coordinated by Atos (Bull SAS). It will run for 3 years with a budget of up to €70 million provided by the EU and the Participating States of the EuroHPC JU.

European Pilot for Exascale (EUPEX)

EUPEX was launched on 1st January 2022 and will develop the first European platform for HPC, gathering and integrating the full breadth of European technologies, from system architecture, processor, system software and development tools, all the way to applications. The EUPEX platform will be a production-grade prototype designed to be open and scalable, and leveraging the HPC technologies used and developed by its scientific and industrial partners. The pilot system will also serve as a development vehicle for software and applications in collaboration with European key user communities.

EUPEX aims to directly support an emerging and vibrant European entrepreneurial ecosystem around European HPC technology, addressing related sectors such as Artificial Intelligence (AI) and Big Data processing. It will be a vehicle to prepare communities working in HPC, AI and Big Data for the upcoming European Exascale systems and federated HPC infrastructure.

The project is coordinated by Atos (Bull SAS). It will run for 4 years with a budget of up to €40.7 million provided by the EU and the Participating States of the EuroHPC JU. EUPEX is linked to The European PILOT through a collaboration agreement to ensure an aligned evolution of European technology towards the next generation of supercomputers.

Pilot using Independent, Local and Open Technologies (The European PILOT)

From 1 December 2021, The European PILOT project (Pilot using Independent, Local and Open Technologies) started working on designing a European accelerator leveraging and extending developments within the framework partnership agreement in European low-power microprocessor technologies.

Accelerators typically provide most of the nominal floating-point performance in modern HPC systems and represent fundamental building blocks of current and future Exascale HPC systems. The European PILOT will demonstrate an accelerator on the basis of European technology and an open standard using the RISC-V instruction set architecture. The integration of accelerators into a highly dense pilot HPC system with liquid immersion cooling technologies will be an important contribution to the European HPC ecosystem.

The project is coordinated by the Barcelona Supercomputing Center (BSC) and brings together multiple partners to combine existing intellectual property with novel innovation as building blocks for future HPC systems.  The project will run for a period of 42 months with a budget of up to €30 million provided by the EU and the Participating States of the EuroHPC JU. The European PILOT is linked to EUPEX through a collaboration agreement to ensure an aligned evolution of European technology towards the next generation of supercomputers.

About the EuroHPC JU

The EuroHPC JU was created in 2018 and recently reviewed by means of Regulation Council Regulation (EU) 2021/1173. 30 European countries are currently taking part in the initiative and pooling their resources with the EU and private partners to enable the EU to become a world leader in supercomputing.

The mission of the EuroHPC JU is to develop, deploy, extend and maintain an integrated world-class supercomputing and data infrastructure in the EU and to develop and support a highly competitive and innovative HPC ecosystem.

• The European Processor Initiative (EPI) has successfully completed its first three-year phase, delivering cutting-edge technologies for European sovereignty on time and within a limited budget, despite the constraints of the COVID-19 pandemic
• Highlights include the Rhea general-purpose processor, EPI accelerator proof of concept and embedded high-performance microcontroller for automotive applications
• The successful completion of this phase, SGA1, paves the way for the second instalment of the project, which kicks off in January 2022

The European Processor Initiative (EPI), a project with 28 partners from 10 European countries aiming to make the EU achieve independence in high-performance computing (HPC) chip technologies and infrastructure, is proud to present key results achieved in phase one (2018-2021).

These results stem from three major research and innovation domains, the General-Purpose Processor (GPP), Accelerator (EPAC) and Automotive streams, complemented by a number of common activities.

General-Purpose Processor (GPP)

Atos, a global leader in digital transformation, cybersecurity, cloud and HPC, is the lead partner of the General-Purpose Processor (GPP) stream. Together with SiPearl, the company bringing to market the high-performance and low-power European processor, and other EPI partners, they defined the architectural specifications of Rhea, the first generation of the EPI General-Purpose Processor (GPP) implementation and its future derivates.

With 29 RISC-V cores, the Arm Neoverse V1 architecture used by SiPearl to design Rhea will offer an effective, scalable and customisable solution for HPC applications. Architectural decisions were taken following a co-design methodology and by analysing the performance of advanced intellectual property (IP) blocks. A scalable network-on-chip (NoC) to enable high-frequency, high-bandwidth data transfers between cores, accelerators, input / output (IO) and shared memory resources was also optimised by SiPearl.

To allow early software development and performance estimation of the EPI processor while the GPP was still at the implementation stage, a GPP virtual prototype was designed and used.

“We are proud of our success in designing a powerful GPP leveraging cutting edge technologies and IPs built and deployed exclusively by European universities and industrial leaders. We are confident that we will soon demonstrate the instrumental role of this GPP in enabling a European exascale computing machine, the next breakthrough in the HPC domain the world is expecting.” – said Stream Leader Emmanuel Ego (Atos).

“At SiPearl, we are very proud to bring to life the joint project of the European Processor Initiative. We worked hard through close collaboration with the initiative’s 28 partners – the scientific community, supercomputing centres, leading names from industry and innovative start-ups – who are our stakeholders, future users, and clients. With the release of the Rhea processor, we will all contribute to ensure European sovereignty in HPC applications such as personalised medicine, climate modelling, and energy management.” – said Philippe Notton, founder and CEO of SiPearl.

Rhea will integrate technologies by EPI partners and offers unique features in terms of memory architecture, memory bandwidth optimisation, security, and power management.

Memory

Memory controllers are one of the most critical IPs when it comes to GPP performance. To help evaluate architectural choices, CEA developed a complete simulation platform with specific instrumentations to analyse controller efficiency in driving the high-bandwidth HBM2E memories. The platform allows efficient analysis of the memory device interface thanks to the decoding and tracking of all memory commands and data. The HBM2E subsystem was simulated with multiple random and directive patterns targeting different traffic shapes and involving all the controller features in maintaining the HBM2E efficiency.

Security

A number of state-of-the-art embedded security features and key technologies were also designed in this stream. These include the standalone Security Management System (SMS) security IP developed by ProvenRun, providing advanced, common-criteria certified, sovereign security IP for HPC and edge processors.

To further bolster security, the University of Pisa contributed a set of crypto IPs, called “Crypto Tile”, integrated in the Rhea GPP by SiPearl. This provides a hardware security module with full security services for high-end symmetric (AES with 9 cipher modes), asymmetric (ECC, ECDSA, ECIES, ECDH) and hashing (SHA2/SHA3) cryptography, delivering several orders of magnitude of increased throughput and decreased energy cost as compared to a software solution.

The Crypto Tile also includes secure key storage and secure IP configuration, side-channel attack protection, on-chip true random number generation (TRNG), support of Linux kernel drivers, extreme key lengths for maximum security levels and high speed en(de)cryption throughput thanks to AXI4-based interface towards DMA and Arm or RISC-V programmable cores. Post-quantum cryptographic support is also provided thanks to real-time implementation of Lattice algorithms such as Crystals Kyber and Dilithium.

Power

Given the importance both of reducing the carbon footprint of future generation computing systems and enabling higher computation capabilities in post-Dennard scaling electronics, energy-efficient computing has been a key consideration in EPI from the outset. For this purpose, an open-source, RISC-V based power controller was designed by University of Bologna and ETH Zurich and integrated into the Rhea processor, harnessing advanced control and artificial intelligence (AI) algorithms for the power management of large-scale systems-on-chip (SoCs).

In addition, based on STMicroelectronics technology on power solutions, Atos and E4 Computer Engineering designed and manufactured the Voltage Regulator and Management reference platform to test the Board Management Controller (mapped inside a field-programmable gate array, or FPGA).

EPI GPP has achieved register transfer level (RTL) completion status as a result of the first phase of the EPI project. The Rhea full design implementation is currently at the validation stage using emulations.

The main result of general-purpose processor activities in EPI phase one, the Rhea processor, will be instrumental for the launch of European exascale supercomputers in 2023.

Accelerators

The EPI accelerator stream set out to deliver energy-efficient acceleration for HPC and AI workloads. With the European Processor Accelerator (EPAC) test chip proof of concept, EPI has demonstrated that it is possible to create an exclusively European design, while the use of open-source instruction-set architectures (ISAs) ensures freedom from proprietary licences and export restrictions.

This stream has fully embraced the open-source philosophy of give and take, contributing to the expansion of the RISC-V ecosystem and adding to the LLVM compiler database. The EPAC systems and FPGA software development vehicles make full use of the Linux operating system and contribute to the community with patches, device drivers, and additional functionality to popular open-source HPC software packages such as OpenMP and MPI. Furthermore, parts of the hardware such as the STX (stencil/tensor accelerator) were developed using a permissively licensed open-source approach around the PULP platform.

“The accelerator stream in EPI has emphatically proven that the RISC-V vector approach has the potential to transform the HPC sector, with designed-in-Europe architectures capable of delivering high performance on a low energy budget,” commented Stream Leader Jesús Labarta (Barcelona Supercomputing Center). “The work also epitomizes European traditions of open science and collaboration. Partners across Europe have joined forces to create something that no single organization could have achieved by itself. By working with open-source technologies and projects, the EPAC stream has helped expand the RISC-V ecosystem, making this technology viable for an increasing number of applications in the future.”

Figure 1 EPAC Test Chip on a test PCB

EPAC set out to provide a proof of concept for European-designed, RISC-V vector architectures for HPC acceleration. A suite of technologies has been developed to this end:

• The EPAC vector processing unit (VPU), design by BSC and UNIZG, shows the use of RISC-V long-vector architectures for high-performance computing is a viable approach, delivering high performance on a low energy budget, and that it can be scaled up in future.
• The vector unit is driven by Semidynamics’ vector-specialised Avispado RISC-V core and Gazzillion Misses™ technology for energy-efficient processing.
• The dedicated and flexible RISC-V based many-core stencil and tensor accelerator (STX), designed by ETH Zurich and Fraunhofer, leverages stencil processing units to offer exceptional energy efficiency and programmability for machine-learning and stencil workloads.
• Meanwhile, the variable precision accelerator (VRP), designed by CEA, enhances efficiency and reliability for scientific high-performance computing applications such as multiphysics simulations.
• The EPAC test chip also includes multiple distributed banks of shared L2 cache and coherence home nodes (L2HN) designed by FORTH and CHALMERS and optimised for the high-bandwidth requirements of the vector processing units while offering a coherent view of the memory system that facilitates multi-core programmability.
• All the processing units and the shared L2HN banks are connected via a high-speed NoC in a modular manner that permits the system to scale up. The test chip also includes advanced SERDES technology for very high-bandwidth off-chip and cross-chip communication. Both the NoC and SERDES were designed by Extoll.
• The PCB (daughter board) to enable the testing of the EPAC Test Chip was designed and developed by E4 Computer Engineering.

EPAC offers exceptional programmability, with generic codes being run successfully on the test chip with minimal modifications and a software development vehicle to support programmers. It is a genuine example of co-design, with a continuous integration system and rapid application of improvements in response to feedback.

Automotive

Coordinated by Infineon, a leader in automotive microcontrollers, the Automotive Stream has paved the way towards road-capable autonomous cars, thanks to the proof of concept for an innovative embedded high-performance compute (eHPC) platform and associated software development kit (SDK). This platform, in combination with a downsized, vehicle-tailored, general-purpose processor, meets the increasing demand for computing power in future cars in a cost-efficient, economically viable and functionally safe way.

“Overall, the achievements are evidence of collaboration, synergies and the team spirit which characterised the research work in the automotive stream”, – said Stream Leader Knut Hufeld (Infineon). “With its focus on cost-effective, safe and certified automotive solutions, it can be seen as a driving belt for the overall profitability of European processors in the field of HPC.”

Figure 2: BMW X5 EPI Test Car and the EPI computing system in the rack.

The main achievement was demonstrated in a road-approved BMW X5 car to show the proof of concept for a pioneering eHPC Microcontroller Unit (eHPC MCU) which is integrated in a specially designed flexible modular computing platform (MCP) together with several EPI technology IPs. Numerous test drives were performed to collect data and evaluate test scenarios involving parameters of autonomous driving.

Among other features, the platform includes AI-supported integrated cameras and Elektrobit radar imaging analysis software, with integrated preparation for use of EPI accelerators in the system. It is the result of a close cooperation among the 16 partners in Stream4 aiming to fulfil its objectives of specifying a suitable eHPC Platform, define its architecture and develop the necessary software development kit (SDK).

Infineon also expanded the automotive microcontroller in terms of its architecture and performance ability so that it can act as master and control one or several accelerators. Relevant aspects were safety, security, fall back or redundancy for reduced application, with regard to the top Automotive Safety Integrity Level D (ASIL D) at system level, which is required for autonomous driving applications.

The platform is scalable and open for further technologies. The MCP has various slots for other technologies developed as part of EPI, including:

• future automotive versions of the EPI general purpose processor
• the EPAC RISC-V based accelerator
• the Kalray Massively Parallel Processor Array (MPPA®) accelerator tile for eHPC, developed as an IP in the Stream 2 and demonstrated for object detection using Kalray’s MPPA®-based Coolidge™ processor for final BMW automotive demonstration
• the Menta eFPGA

Test runs reveal that EPI now has specific technologies suitable for autonomous driving up to at least level 4 – where the vehicle drives independently most of the time – thus paving the way for the future.

In addition to the hardware platform, this stream also included the development of a complete software ecosystem, based to a large extent on software products by automotive software specialist Elektrobit. This area also comprises the automotive eHPC platform software stack, including the classic automotive open operating system architecture (AUTOSAR) development for Auto eHPC MCUs, and the adaptive AUTOSAR development for HPC GPPs and the L4Re hypervisor (virtualisation) that are crucial for automotive applications.

With regard to safety, a specific concept was jointly created for a software lockstep, thus contributing to an overall EPI safety concept.

After this three-year initial phase, the results and findings will be continued in further projects.

Common Activities

This stream acted as a provider for other technical streams. Excellent collaboration, both internally and with other streams, helped mitigate issues caused by pandemic-imposed travel restrictions and allowed the stream to meet its objectives, enumerated below.

This stream established a co-design process to shape the design of European processors. Simulations and models with different levels of detail and precision were created to identify the impact of design decisions on the performance of future applications. A benchmark suite of over 40 applications was used to support co-design and later evaluate the EPI processors. Applications have also been prepared to run on future EPI systems, by adapting and testing them on comparable hardware platforms and emulators.

The specification of a “common platform” architecture was defined and used as a backbone for architecture exploration, as the starting point for the GPP implementation, and to define guidelines for security and heterogeneous integration.

Another major result was the integration of the power management design in the GPP specifications: power management firmware, off-chip integration consolidating power distribution board design, PLDA integration, and consolidation of the power management hardware integration.

Work was also done on multiple aspects of the support of system software development: general and hybrid programming environments, OpenMP and MPI runtimes on both GPP and RISC-V sides, OpenMP extra threads support for dynamic load balancing (DLB) and the introspection-based scheduling mechanism in the LLVM OpenMP runtime, offloading for both GCC and LLVM toolchains, testing of power and energy monitoring libraries on available reference ARM Platform, and the resource manager.

Another notable achievement was the development of three tools – gem5, MUSA and SESAM/VPSim – for a complete multi-level simulation environment that provides relevant virtual prototypes for a wide range of needs encountered in the EPI streams. These tools demonstrated broad capabilities, including detailed chiplet- and NoC-level simulation, system simulation for software design, and performance evaluation for design space exploration and hardware co-design activities.

• JUELICH and FORTH jointly developed a gem5 simulation package of Rhea. This cycle-accurate computer architecture simulator is capable of modelling a variety of hardware platforms. It provides models of varying complexity for CPU cores, memory devices, coherent caches and on-chip networks, which can be combined in a modular fashion.
• MUSA, from BSC, relies on native execution traces with two levels of detail to allow simulation of different communication networks, numbers of cores per node, and relevant microarchitectural parameters. In addition, MUSA incorporates support for register renaming using a register file of any generic size as well as support for the most advanced cache prefetchers (e.g., BOP, SPP, etc.)
• The CEA development SESAM/VPSim allows collaborations across multiple work packages by being flexible enough in its capabilities to operate alone, to interface with third-party physical system platforms or simulators, and to be integrated with most of the virtual prototyping methodologies used in the EPI project. Moreover, SESAM/VPSim includes fast on-chip network and cache performance models as well as decoupling the simulation of functional and extra-functional behaviours, resulting in a good compromise between accuracy and simulation time.

“I was delighted to take over the management of a successful stream, midway through the project, that was able to provide a very high level of co-design, a comprehensive set of benchmarks, and useful simulation platforms that allowed the project to envision processor architecture, effective power management, and to start delivering libraries fit for the new system. I would like to thank Romain Dolbeau, who started the stream, and all the work package leaders and teams for their passion and kind spirit of collaboration.” – said Stream Leader Jean-François Blanc (Atos).

The outlook

“I’m proud of the outstanding results achieved by EPI teams after only three years of cooperation, paving the way towards Europe’s technological sovereignty. I’m particularly impressed we delivered our objectives on time with a limited budget, despite the unprecedented working conditions due to the terrible COVID-19 pandemic. This has created favourable conditions for the launch of the next phase and its successful delivery of the European processors and accelerators for the EUPEX (EUropean Pilot for Exascale) and TEP (The European Pilot) projects, the precursors to European exascale systems.” – said Eric Monchalin (Atos), chairman of the EPI Board.

About EPI

The European Processor Initiative (EPI) is a project currently implemented under the first stage of the Framework Partnership Agreement signed by the Consortium with the European Commission (FPA: 800928), whose aim is to design and implement a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

Another step closer to demonstrate the capabilities of a RISC-V based European microprocessor

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.

One key segment of EPI activities is to develop and demonstrate fully European-grown processor IPs based on the RISC-V Instruction Set Architecture, providing power-efficient and high-throughput accelerator cores named EPAC (European Processor Accelerators).

EPAC combines several accelerator technologies specialized for different application areas. The test chip, shown in the figure below, contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The chip also includes two additional accelerators: the Stencil and Tensor accelerator (STX) designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. All accelerators on the chip are connected with a very high-speed network on chip and SERDES technology from EXTOLL.

The 143 packaged EPAC test chip samples were fabricated in GLOBALFOUNDRIES 22FDX low-power technology, have an area of 26.97mm², 14 million placeable instances (93M Gate Equivalent) including 991 memory instances, are packaged in FCBGA with 22×22 balls and have a target frequency of 1GHz.

Figure 1 EPAC test samples

Initial bring-up was successful and EPAC executed its first bare metal program sending the traditional “Hello World!” greetings in different languages to EPI consortia and the world!

Figure 2 Hello World! screenshot

The outlook

EPI will continue to develop, optimize and validate different IP blocks and demonstrate features and performance of those thus creating an EU HPC IP ecosystem and make it available to the processor and accelerator industry and academia to create globally competitive production class building blocks for the next generation HPC systems.

On July 19th, the Council Regulation establishing the European High-Performance Computing Joint Undertaking was published in the Official Journal of the European Union. It was formally adopted on July 13th, by the Economic and Financial Affairs Council.

This is an important piece of news for the HPC community, opening up EuroHPC JU’s ability to draw funds from the Horizon Europe, Digital Europe and the Connecting Europe Facility programmes. The news item and full regulation text can be found on the EuroHPC JU’s website, here:

https://eurohpc-ju.europa.eu/press-releases/eurohpc-ju-regulation-published-official-journal-european-union.

General Assembly of European Processor Initiative has selected a new Chairman of the Board in July. Eric Monchalin from Atos, the company that coordinates the EPI project, is going to lead 28 partners from 10 countries in their efforts to design and implement a roadmap for a new family of low-power European processors.

Eric is experienced in leading 100+ people organizations and managing multi tens millions of Euros projects in international environments. He is a technology-minded person who values wide range of skills and technological knowledge focused on customer expectations to turn them into reality. Furthermore, Eric’s career has been mainly built on numerous Hardware and Software R&D positions in several companies and various domains like signal processing, embedded systems, communication, storage, High Performance Computing and Artificial Intelligence.

Taking place on 30 August – 3 September 2021, the second ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications will be co-hosted by Barcelona Supercomputing Center (BSC), in conjunction with the Universitat Politècnica de Catalunya – Barcelona Tech (UPC).

The programme of this year’s summer school, which will be fully remote, centres around topics within the European Processor Initiative. Open hardware expert Luca Benini (ETH Zürich / University of Bologna) will be discussing machine learning from a RISC-V platform perspective, while the EPI Accelerator stream leader Jesús Labarta (BSC) will train attendees in performance analysis and hybrid programming, helping them get the very best out of their code. Meanwhile, Mauro Olivieri (Sapienza – University of Rome / BSC) will present vector acceleration in high-performance computing (HPC) and edge devices.

Keynote talks will be given by celebrated computer scientists and engineers including Luca Cardelli (Oxford University), Bill Dally (Stanford University / NVIDIA), Mihaela van der Schaar (Cambridge University) and Mateo Valero (BSC). There will also be invited talks by EPI researchers Roger Espasa (Semidynamics) on the RISC-V Avispado core, John Davis (BSC) on building an open-source ecosystem for HPC, and Marc Casas (BSC) on accelerating deep neural network training.

The school chairpersons are Mateo Valero and Josep Fernandez (UPC), while the local organizing committee is led by Eduard Ayguadé, (BSC and UPC), and Fabrizio Gagliardi (BSC and ACM).

“EPI is revolutionising computer architecture to pave the way for Europe’s technological sovereignty. As part of the EPI training programme, this summer school provides the ideal introduction to some of the initiative’s main themes,” commented Jean-Marc Denis (Atos / SiPearl), chairman of the EPI board.

Upon completion of the school, all attendees will receive a certificate and a complimentary ACM student membership. Based on the scores obtained in the practical exercises, the best performing students will receive a certificate of honour and will also invited to interviews with industry sponsors, with a view to a possible internship.

The school includes a poster session, with a prize for the best poster.

Registration will be open until 15 July, and accepted candidates will be informed by 1 August.

To register, complete the registration form on the ACM Europe website.

The Initiative has successfully released EPAC1.0 Test Chip for fabrication

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of helping the EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that we have successfully released our EPAC1.0 Test Chip for fabrication.

One key segment of EPI activities is to develop and demonstrate fully European-grown processor IPs based on the RISC-V Instruction Set Architecture, providing power-efficient and high-throughput accelerator cores named EPAC (European Processor Accelerators). Using the RISC-V Instruction Set Architecture will allow leveraging open-source resources at hardware architecture and software level, as well as ensure independence from non-European patented computing technologies.

EPAC combines several accelerator technologies specialized for different application areas. The test chip, shown in figure 1 below, contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The Stencil and Tensor accelerator (STX) was designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. These specialized accelerators are connected with very high-speed network on chip and SERDES technology from EXTOLL.

The EPAC design was finalized by Fraunhofer IIS for chip integration in GLOBALFOUNDRIES 22FDX low-power technology and will be integrated and evaluated in the FPGA-based board designed by FORTH, E4 and the University of Zagreb. The successful fabrication of EPAC will showcase the next step in accelerator-based green HPC computing.

Figure 1 EPAC layout with VPU, STX and VRP accelerators with 25 mm2 in GF 22FDX technology

The outlook

The next generation of the EPAC accelerators and interfaces will be improved and refined for even higher performance and lower power levels in 12 nm technologies and below, and by adding a chiplet approach.

Jesus Labarta, BSC (EPAC Coordinator): I am really happy how partners with different backgrounds and motivations have been able to collaboratively develop this chip, putting all their efforts towards a collective success. It is a fully European design, driven by a vision of throughput-oriented computing and featuring characteristic that will result in high programmer productivity and achieve very high performance at low power and cost. Although just an initial Test Chip, it can be a significant step forward in HPC but also for edge and embedded applications.

Norbert Schuhmann, Fraunhofer IIS: The key challenge in this design and architecture was not only to achieve highest throughput and low power levels within the accelerators running on more than 1 GHz, but also to be in sync like in a concerto with memory accesses and data transport inside the chip and to the peripherals at rates above 200 Gbit/s.